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XC7A75T-1FGG484I鏄疿ilinx鍏徃鎺ㄥ嚭鐨凙rtix-7绯诲垪FPGA鑺墖锛屽爆浜庨珮绔�7绯诲垪鍙法绋嬮倧杓櫒浠朵箣涓�銆傝┎鍨嬭櫉鍏锋湁楂樻�ц兘銆佷綆鍔熻�楀拰璞愬瘜鐨勮硣婧愮壒榛�锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆佽闋昏檿鐞嗕互鍙婇啱(y墨)鐧傛垚鍍忕瓑闋樺煙鐨勫京闆滆ō瑷堜换鍕欍��
銆�銆�Artix-7绯诲垪閲囩敤28nm鍒剁▼宸ヨ棟锛岃兘澶犳彁渚涢潏娲荤殑鍙法绋嬭兘鍔涜垏楂樻�у児姣旇В姹烘柟妗堛�俋C7A75T鍦ㄥ収(n猫i)閮ㄩ泦鎴愪簡璞愬瘜鐨勯倧杓柈鍏冿紙Slice锛�銆丏SP妯″銆丷AM濉婁互鍙婇珮閫熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑绲勪欢锛屽悓鏅傛敮鎸佸绋厤缃ā寮忓拰鎺ュ彛妯欐簴銆�
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銆�銆�灏佽褰㈠紡锛欶GG484
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�FPGA绯诲垪锛欰rtix-7
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細75,400鍊婼lice
銆�銆�DSP Slice鏁�(sh霉)閲忥細180鍊�
銆�銆�Block RAM瀹归噺锛氱磩1.3MB
銆�銆�灏堢敤鏅傞悩璩囨簮锛�8鍊婱MCM+2鍊婸LL
銆�銆�鐢ㄦ埗I/O寮曡叧鏁�(sh霉)锛�316
銆�銆�宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C鑷�+100掳C锛�
銆�銆�渚涢浕闆诲锛氬収(n猫i)鏍�1.0V锛岃紨鍔�1.8V/3.3V
銆�銆�閰嶇疆妯″紡锛歁aster SPI銆丼lave SPI銆丅PI銆丣TAG
XC7A75T-1FGG484I鍏峰倷寮峰ぇ鐨勬�ц兘鍜岄潏娲绘�э細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧愶細75,400鍊婼lice鎻愪緵浜嗚冻澶犵殑閭忚集瀹归噺渚嗗鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺��
銆�銆�280鍊嬪皥鐢―SP Slice鍙互楂樻晥瀹屾垚涔樻硶绱姞閬嬬畻锛岄潪甯搁仼鍚堜俊铏熻檿鐞嗘噳鐢ㄣ��
銆�銆�3. 澶у閲忓瓨鍎茶硣婧愶細鍖呮嫭Block RAM鍜孌istributed RAM锛岀附?c猫)钀樼獰_鍒扮磩1.3MB锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╁瓨鎴栨煡鎵捐〃鍔熻兘銆�
銆�銆�4. 楂橀�熷樊鍒咺/O锛氭敮鎸侀珮閬�1.25Gbps鐨凩VDS閫熺巼锛屾豢瓒崇従(xi脿n)浠ｆ帴鍙ｉ渶姹�銆�
銆�銆�5. 浣庡姛鑰楁灦妲嬶細閲囩敤Intelligent Power-Gating鎶�琛撳拰鍙畩闋荤巼鏅傞悩绠＄悊浠ユ笡灏戦潨鎱�(t脿i)鍙婂嫊鎱�(t脿i)鍔熻��銆�
銆�銆�6. 闈堟椿閰嶇疆閬搁爡锛氭敮鎸佸绋暉鍕曟柟寮�锛屽苟鍙�氶亷澶栫疆闁冨瓨杓曟澗瀵︾従(xi脿n)绯荤当(t菕ng)鏇存柊銆�
銆�銆�7. 寮峰ぇ鐨勬檪閻樼鐞嗗伐鍏凤細闆嗘垚澶氬�嬪璺京鐢ㄥ櫒閹栫浉鐠�(hu谩n)锛圡MCM锛夎垏鐩镐綅閹栧畾鐠�(hu谩n)锛圥LL锛�锛岀⒑淇濈簿纰虹┅(w臎n)瀹氱殑鏅傞悩鍒嗛厤銆�
銆�銆�8. 鍙潬鎬у寮凤細鍏�(n猫i)缃嚜妾㈡鍒跺拰閷鏍℃鍔熻兘锛屾彁楂樻暣楂旂郴绲�(t菕ng)绌�(w臎n)瀹氭��銆�
瑭叉FPGA閬╃敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛氬鍦栧儚閲囬泦鍗°�侀珮娓呮敐鍍忛牠铏曠悊鍠厓銆�
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銆�銆�5. 娓│娓噺骞宠嚭锛氶牷璀滃垎鏋愬剙鍓嶇淇¤櫉瑾�(di脿o)鐞嗛浕璺�銆�
銆�銆�6. 寤ｆ挱绱氳闋诲垏鎻涜嚭锛氬鏅傛祦濯掗珨绶ㄧ⒓瑙ｇ⒓铏曠悊銆�
銆�銆�7. 绉戝鐮旂┒浠跨湡锛氱墿鐞嗗椹楁暩(sh霉)鎿�(j霉)閲囬泦鑸囧垵姝ヨ▓绠�銆�
XC7A50T-1FGG484I
銆�銆�XC7A100T-1FGG484I
