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闁辫畝锛�33
XC7K325-1FBG900I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴娆剧敘鍝�銆侫rtix-7 绯诲垪鏄� Xilinx 7 绯诲垪 FPGA 鐨勬垚鍝′箣涓�锛屽皥鐐轰綆鍔熻�楀拰楂樻�ц兘鎳夌敤鑰岃ō瑷�銆傝┎鍣ㄤ欢閲囩敤 28nm 宸ヨ棟鍒堕��锛屾彁渚涜睈瀵岀殑閭忚集璩囨簮銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″銆佸瓨鍎插櫒璩囨簮浠ュ強澶氱ó鎺ュ彛閬搁爡銆俋C7K325T-1FBG900I 涓殑 '325' 琛ㄧず鍏堕倧杓柈鍏冭(gu墨)妯�锛�'1' 琛ㄧず閫熷害绛夌礆锛�'FBG900' 琛ㄧず灏佽椤炲瀷鍙婂紩鑵虫暩(sh霉)锛�'I' 琛ㄧず鍟嗘キ(y猫)绱氬伐浣滄韩搴﹁寖鍦�銆�
銆�銆�瑭插瀷铏熺殑 FPGA 闈炲父閬╁悎鐢ㄤ簬閫氫俊銆佹秷璨婚浕瀛�銆侀啱(y墨)鐧傛垚鍍�銆佸伐妤�(y猫)鑷嫊鍖栫瓑闋樺煙鐨勫京闆滄暩(sh霉)瀛楅浕璺ō瑷�銆�
閭忚集鍠厓锛�325,200
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丅PI
銆�銆�RAM锛�16MB
銆�銆�DSP Slice锛�840
銆�銆�I/O 鏁�(sh霉)閲忥細464
銆�銆�鏅傞悩绠＄悊 tile锛�
銆�銆�宸ヤ綔闆诲锛�1.0V 鏍稿績闆诲 / 1.8V I/O 闆诲
銆�銆�灏佽锛欶BG900
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C
XC7K325-1FBG900I 鎻愪緵浜嗛珮搴﹂潏娲荤殑鍙法绋嬮倧杓祼妲�锛岄仼鐢ㄤ簬鍚勭ó寰╅洔绯荤当(t菕ng)瑷▓銆�
銆�銆�1. 楂樻�ц兘鏋舵锛氬熀浜� UltraScale 鏋舵鍓嶄竴浠ｇ殑 Artix-7 绯诲垪 FPGA 鎻愪緵浜嗗嚭鑹茬殑鎬ц兘锛屾敮鎸侀珮閬� 6.6 Gbps 鐨勪覆琛屾敹鐧�(f膩)鍣ㄩ�熺巼銆�
銆�銆�2. 浣庡姛鑰楋細閲囩敤 28nm HPL锛堥珮鎬ц兘浣庡姛鑰楋級宸ヨ棟鎶�琛擄紝椤憲闄嶄綆浜嗗嫊鎱�(t脿i)鍜岄潨鎱�(t脿i)鍔熻��锛屽悓鏅備繚璀夐珮鎬ц兘銆�
銆�銆�3. 澶у閲忓瓨鍎诧細鍖呭惈澶氶仈 16MB 鐨勭墖涓� Block RAM锛岃兘澶犳豢瓒冲京闆滅殑绠楁硶鍜屾暩(sh霉)鎿�(j霉)绶╂矕闇�姹�銆�
銆�銆�4. 寮峰ぇ鐨� DSP 鍔熻兘锛氶泦鎴愪簡 840 鍊� DSP Slice锛屽彲鐢ㄤ簬楂橀�熸暩(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�锛屽婵炬尝銆丗FT 鍜岀煩闄ｉ亱绠楃瓑銆�
銆�銆�5. 澶氭ǎ鍖栫殑 I/O 鎺ュ彛锛氭敮鎸� PCIe銆佸崈鍏嗕互澶恫銆丼ATA 绛夊绋珮閫熸帴鍙ｅ崝(xi茅)璀�銆�
銆�銆�6. 鍏х疆鏅傞悩绠＄悊锛氭彁渚涗簡 6 鍊嬫檪閻樼鐞� tile锛屾敮鎸� PLL 鍜� MMCM锛屽彲浠ュ鐝�(xi脿n)绮剧⒑鐨勬檪閻樺垎闋诲拰鍊嶉牷鍔熻兘銆�
銆�銆�7. 鍙潬鎬э細鏀寔鍏х疆鑷鍔熻兘鍜岄尟瑾ゆ娓鍒�锛岀⒑淇濈郴绲�(t菕ng)鐨勭┅(w臎n)瀹氶亱琛屻��
XC7K325-1FBG900I 寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 閫氫俊锛氱敤浜庣劇绶氬熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊鍜屽崝(xi茅)璀拌綁鎻涖��
銆�銆�2. 娑堣不椤為浕瀛愮敘鍝侊細鍦ㄩ珮娓呰闋昏檿鐞�銆佸湒鍍忚瓨鍒ュ拰闊抽牷铏曠悊鏂归潰鐧�(f膩)鎻噸瑕佷綔鐢�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬瓒呰伈娉㈣ō鍌欍�丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傚剙鍣ㄧ殑鏁�(sh霉)鎿�(j霉)閲囬泦鍜屽湒鍍忛噸寤�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)閬嬪嫊鎺у埗銆佹鍣ㄤ汉瑕栬鍜屽鏅傛暩(sh霉)鎿�(j霉)鍌宠几?sh霉)瑁櫸村爧?br>銆�銆�5. 姹借粖闆诲瓙锛氱敤浜庨珮绱氶椐涜紨鍔╃郴绲�(t菕ng) (ADAS) 鍜岃嚜鍕曢椐涚浉闂滅殑绠楁硶鍔犻��銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細閬╃敤浜庨浄閬斾俊铏熻檿鐞�銆佽(w猫i)鏄熼�氫俊绛夊皪鍙潬鎬ц姹傛サ楂樼殑鍫存櫙銆�
XC7K325T-2FBG900I
銆�銆�XC7K325T-3FBG900C
