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XC7K325T-1FB676I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍝�銆傝┎鍣ㄤ欢鍩轰簬 28nm 宸ヨ棟鎶�琛�锛屽叿鏈夐珮鎬ц兘銆佷綆鍔熻�楃殑鐗归粸锛岄仼鐢ㄤ簬閫氫俊銆佸伐妤�(y猫)鎺у埗銆侀啱(y墨)鐧傝ō鍌欍�佽闋昏檿鐞嗙瓑澶氬�嬮牁鍩�銆�
銆�銆�Artix-7 绯诲垪 FPGA 鎻愪緵浜嗚睈瀵岀殑閭忚集璩囨簮鍜� DSP 妯″锛屾敮鎸侀珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犳豢瓒冲绋京闆滄噳鐢ㄧ殑闇�姹�銆俋C7K325T 鐗瑰垾閬╁悎闇�瑕侀珮瀵嗗害閭忚集闆嗘垚鍜屼綆鍔熻�楃殑鍫存櫙銆�
鍨嬭櫉锛歑C7K325T
銆�銆�灏佽锛欶BGA 676 鐞�
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�宸ヨ棟鎶�琛擄細28nm
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SPI, SelectMAP
銆�銆�I/O 寮曡叧鏁革細314
銆�銆�鐢ㄦ埗鍙敤 I/O 鏁搁噺锛�290
銆�銆�閭忚集鍠厓鏁搁噺锛�325,200
銆�銆�DSP Slice 鏁搁噺锛�840
銆�銆�Block RAM 绺藉閲忥細12.4Mb
銆�銆�灏堢敤鏅傞悩璩囨簮锛�16 鍊� MMCM 鍜� 16 鍊� PLL
銆�銆�鏈�澶у伐浣滄韩搴﹁寖鍦嶏細-40掳C 鑷� +100掳C
XC7K325T-1FB676I 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛屾敮鎸侀珮閬� 667MHz 鐨勭郴绲�(t菕ng)鏅傞悩闋荤巼銆�
銆�銆�2. 鍏х疆璞愬瘜鐨� DSP Slice锛岄仼鐢ㄤ簬鍚勭ó鏁稿瓧淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�3. 鎻愪緵澶氶仈 16 鍊嬫贩鍚堟ā寮忔檪閻樼鐞嗘ā濉婏紙MMCM锛�锛屾敮鎸佸嫊鎱�(t脿i)鐩镐綅瑾挎暣鍜屾檪閻樺�嶉牷/鍒嗛牷銆�
銆�銆�4. 鏀寔鏈�楂� 6.6Gbps 鐨� GTX 鏀剁櫦(f膩)鍣�锛岀敤浜庨珮閫熸暩鎿氬偝杓搞��
銆�銆�5. 閲囩敤 28nm HPL锛圚igh Performance with Low Power锛夊伐钘�锛岄’钁楅檷浣庡姛鑰椼��
銆�銆�6. 鎻愪緵闈堟椿鐨勯厤缃伕闋�锛屽寘鎷� Slave Serial銆丮aster SPI 鍜� SelectMAP 绛夋ā寮�銆�
銆�銆�7. 鍏ч儴闆嗘垚浜嗗ぇ瀹归噺 Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屾豢瓒冲京闆滅畻娉曠殑瀛樺劜闇�姹�銆�
銆�銆�8. 鏀寔閮ㄥ垎閲嶉厤缃姛鑳�锛屽厑瑷卞湪閬嬭鏅傚皪閮ㄥ垎鍗�(q奴)鍩熼�茶閲嶆柊绶ㄧ▼銆�
銆�銆�9. 鎻愪緵鍏ㄩ潰鐨勮ō瑷堝伐鍏锋敮鎸侊紝鍖呮嫭 Vivado Design Suite 鍜� ISE Design Suite銆�
XC7K325T-1FB676I 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛氬宸ユキ(y猫)鐩告銆侀啱(y墨)鐢ㄦ垚鍍忚ō鍌欑瓑銆�
銆�銆�2. 鏁告摎閫氫俊锛氬寘鎷恫绲′氦鎻涙銆佽矾鐢卞櫒鍜岀劇绶氬熀绔欑瓑銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細濡傚鏅傛帶鍒剁郴绲�(t菕ng)銆侀亱鍕曟帶鍒跺櫒绛�銆�
銆�銆�4. 閱�(y墨)鐧傞浕瀛愶細濡傝秴鑱叉尝瑷倷銆丆T 鎺冩弿鍎�绛�銆�
銆�銆�5. 娑堣不椤為浕瀛愮敘鍝侊細渚嬪楂樼闊宠闋昏檿鐞嗚ō鍌�銆�
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細娑夊強闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊绛夐珮鍙潬鎬ф噳鐢ㄥ牬鏅��
銆�銆�7. 浜哄伐鏅鸿兘鎺ㄧ悊鍔犻�熷櫒锛氶�氶亷鍏跺挤澶х殑骞惰瑷堢畻鑳藉姏瀵︾従(xi脿n)绁炵稉缍茬怠鎺ㄦ柗浠诲嫏銆�
XC7K325T-2FB676I
銆�銆�XC7K325T-3FB676I
