鍨嬭櫉(h脿o)锛歑C7K410T-3FBG900I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欿intex-7
銆�銆�灏佽�濓細FBG900
銆�銆�I/O 鏁�(sh霉)閲忥細566
銆�銆�閰嶇疆瀛樺劜(ch菙)鍣ㄩ�炲瀷锛�?ji菐n)鍛�?宸�鍒�
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SelectMAP, Slave BPI, Master SPI
銆�銆�鐢ㄦ埗鍙�鐢ㄩ倧杓�鍠�鍏冩��(sh霉)閲忥細410K
銆�銆�鏈�澶ф煡鎵捐〃 (LUT)锛�245760
銆�銆�瑙哥櫦(f膩)鍣ㄦ暩(sh霉)閲忥細491520
銆�銆�Block RAM 瀹归噺锛�54Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1020
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細80
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛氭渶楂� 11.4Gbps
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�鏍稿績闆诲�擄��1.0V

1. 楂樻�ц兘鑸囦綆鍔熻�楋細
銆�銆�Kintex-7 绯诲垪閲囩敤 Xilinx 鐨� 28nm High-K Metal Gate 宸ヨ棟鎶�琛�(sh霉)锛屽��(sh铆)鐝�(xi脿n)浜嗗崜瓒婄殑鎬ц兘鍜岃純浣庣殑闈滄厠(t脿i)鍔熻��銆俋C7K410T 鎻愪緵浜嗛珮閬�(d谩) 1020 鍊�(g猫) DSP Slice 鍜� 54Mb 鐨� Block RAM锛岃兘澶犻珮鏁堣檿鐞嗗京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)閬�(y霉n)绠楀拰鏁�(sh霉)鎿�(j霉)瀛樺劜(ch菙)浠诲嫏(w霉)銆�
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銆�銆�3. 璞愬瘜鐨� I/O 璩囨簮锛�
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銆�銆�鐢变簬鍏堕潏娲荤殑鏋舵��(g貌u)鍜屽挤(qi谩ng)澶х殑鎬ц兘锛岄�欐�� FPGA 鍙�浠ュ嫕浠诲緸鐒＄窔閫氫俊鍩虹珯鍒伴珮绔�閱�(y墨)鐧傚奖鍍忕郴绲�(t菕ng)鐨勫悇绋�寰�(f霉)闆滀换鍕�(w霉)銆�

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