鍨嬭櫉(h脿o)锛歑C7K420T-L2FFG901E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欰rtix-7
銆�銆�灏佽�濋��(l猫i)鍨嬶細FFG901
銆�銆�I/O 鏁�(sh霉)閲忥細532
銆�銆�閰嶇疆闁冨瓨锛氱劇(w煤)鍏�(n猫i)閮ㄩ杻瀛�
銆�銆�鏈�澶х敤鎴�(h霉)鍙�鐢ㄩ倧杓�鍠�鍏冿��420,000
銆�銆�Block RAM 瀹归噺锛氱磩 27 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1,080
銆�銆�鏅�(sh铆)閻樿硣婧愶細鏈�澶氭敮鎸� 16 鍊�(g猫) PLL
銆�銆�鏈�灏忓伐浣滄韩搴︼細-40掳C
銆�銆�鏈�澶у伐浣滄韩搴︼細+100掳C
銆�銆�渚涢浕闆诲�擄��0.9V 鏍稿績闆诲�擄��1.0V 杓斿姪闆绘簮

XC7K420T-L2FFG901E 鎻愪緵浜嗗挤(qi谩ng)澶х殑鍙�绶ㄧ▼閭忚集璩囨簮鍜岄潏娲荤殑浜掗�ｆ灦妲�(g貌u)锛屼娇鍏堕仼鐢ㄤ簬澶氱ó寰�(f霉)闆滅殑瑷�(sh猫)瑷�(j矛)闇�姹�銆�
銆�銆�1. 鍩轰簬 UltraScale 鏋舵��(g貌u)鐨勬敼閫�(j矛n)鐗堟湰锛屽叿鏈夋洿楂樼殑閬�(y霉n)琛屾晥鐜囧拰鏇翠綆鐨勫姛鑰�銆�
銆�銆�2. 鍏�(n猫i)缃�璞愬瘜鐨� DSP Slice 鍜� Block RAM锛岃兘澶犳敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏�(h脿o)铏曠悊鍜岀畻娉曞��(sh铆)鐝�(xi脿n)銆�
銆�銆�3. 鏀�鎸佸�氱ó楂橀�熶覆琛屾帴鍙�锛屼緥濡� GTX 鏀剁櫦(f膩)鍣�锛岄�熺巼楂橀仈(d谩) 6.6 Gbps锛屾豢(m菐n)瓒崇従(xi脿n)浠ｉ�氫俊绯荤当(t菕ng)鐨勮�佹��銆�
銆�銆�4. 鎻愪緵闈堟椿鐨勬檪(sh铆)閻樼�＄悊宸ュ叿锛圕lock Management Tile锛�锛屾敮鎸� PLL 鍜� MMCM 妯″�婁��?x煤n)?y艒u)鍖栨檪(sh铆)閻樺垎閰嶃��
銆�銆�5. 鍖呭惈纭�鏍� PCIe Gen2 鍗�(xi茅)璀版帶鍒跺櫒锛屾柟渚胯垏涓绘��(j墨)鎴栧叾浠栧�栬��(sh猫)閫�(j矛n)琛岄珮閫熼�氫俊銆�
銆�銆�6. FPGA 鐨勮ō(sh猫)瑷�(j矛)娴佺▼鍙�浠ュ�熷姪 Vivado Design Suite 鎴� ISE Design Suite 瀹屾垚锛岀啊(ji菐n)鍖栭枊(k膩i)鐧�(f膩)鍛ㄦ湡銆�
銆�銆�7. 宸ユキ(y猫)绱�(j铆)婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C锛変繚璀変簡鍦ㄦサ绔�鐠�(hu谩n)澧冧笅鐨勫彲闈犳��銆�

XC7K420T-L2FFG901E 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬闇�瑕侀珮鎬ц兘鍜屼綆鍔熻�楃殑鍫�(ch菐ng)鏅�锛屽寘鎷�浣嗕笉闄愪簬锛�
銆�銆�1. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細瀵�(sh铆)鏅�(sh铆)鎺у埗銆侀亱(y霉n)鍕�(d貌ng)鎺у埗鍜屾暩(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�2. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鐒�(w煤)绶�(xi脿n)鍩虹珯銆佸皬鍨嬭渹绐╃恫(w菐ng)闂�(gu膩n)銆佷俊铏�(h脿o)瑾�(di脿o)鍒惰В瑾�(di脿o)绛�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈣檿鐞嗗櫒銆丆T 鍦栧儚閲嶅缓銆�
銆�銆�4. 瑕栭牷铏曠悊锛氶珮娓呰�栭牷绶ㄧ��/瑙ｇ⒓銆佸湒鍍忓�炲��(qi谩ng)銆�
銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫燂細姗�(j墨)鍣ㄥ��(xu茅)缈�(x铆)鎺ㄧ悊銆佹暩(sh霉)鎿�(j霉)搴�(k霉)鏌ヨ��(x煤n)鍔犻�熴��
銆�銆�6. 姹借粖(ch膿)闆诲瓙锛氶珮绱�(j铆)椐曢�涜紨鍔╃郴绲�(t菕ng)锛圓DAS锛�銆佽粖(ch膿)杓変俊鎭�濞涙��(l猫)绯荤当(t菕ng)銆�
銆�銆�7. 娓�(c猫)瑭︽脯(c猫)閲忥細绀烘尝鍣ㄨЦ鐧�(f膩)妯″��銆佸崝(xi茅)璀板垎鏋愬剙銆�

XC7K410T-2FFG901I, XC7K420T-2FFG676I