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銆�銆�XC7K480T 灞簬涓鎬ц兘鐨� FPGA锛屽叿鏈夎睈瀵岀殑閭忚集璩囨簮銆丏SP 妯″浠ュ強涓茶鏀剁櫦(f膩)鍣ㄨ硣婧�锛岃兘澶犳豢瓒冲绋京闆滅畻娉曡檿鐞嗗拰鎺ュ彛鍗�(xi茅)璀伴渶姹�銆傚叾 -1 閫熷害绛夌礆琛ㄧず杓冨揩鐨勫伐浣滄檪閻橀牷鐜�锛孎(xi脿n)F901C 鍓囨寚瀹氫簡灏佽椤炲瀷鐐� 901 寮曡叧鐨� FCBGA锛團ine Pitch Ball Grid Array锛夊皝瑁�銆�
鍣ㄤ欢鍨嬭櫉锛歑C7K480T
銆�銆�绯诲垪锛欿intex-7
銆�銆�鍏徃锛歑ilinx
銆�銆�閫熷害绛夌礆锛�-1
銆�銆�灏佽椤炲瀷锛欶F901C
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 480,000
銆�銆�瀛樺劜鍣細22.5 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1,140
銆�銆�涓茶鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬� 6.6 Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 560
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Kintex-7 绯诲垪 FPGA 鎻愪緵浜嗗嚭鑹茬殑鎬у児姣旇垏鎬ц兘琛ㄧ従(xi脿n)銆俋C7K480T-1FF901C 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵锛氶噰鐢� 28nm 宸ヨ棟鍒剁▼锛屽叿鍌欏劒(y艒u)鍖栫殑閭忚集绲愭鍜岄珮鍚炲悙閲忔暩(sh霉)鎿�(j霉)璺緫锛岄仼鍚堝京闆滅殑淇¤櫉铏曠悊浠诲嫏銆�
銆�銆�2. 鍏х疆 DSP 妯″锛氶泦鎴� 1,140 鍊嬮珮鎬ц兘 DSP Slice锛屽彲鍔犻�熸诞榛為亱绠楀拰鐭╅櫍瑷堢畻绛変换鍕欍��
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XC7K480T-1FF901C 寤ｆ硾鐢ㄤ簬闇�瑕侀珮甯跺鍜屽京闆滈倧杓檿鐞嗙殑鎳夌敤鍫存櫙锛屽叿楂斿寘鎷細
銆�銆�1. 鐒＄窔鍩虹瑷柦锛氬 LTE 鍜� 5G 鍩虹珯涓殑淇¤櫉铏曠悊妯″銆�
銆�銆�2. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)姗熷櫒瑕栬銆侀亱鍕曟帶鍒跺拰瀵︽檪鏁�(sh霉)鎿�(j霉)閲囬泦銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉��丆T 鎺冩弿鍎�绛夎ō鍌欎腑鐨勫湒鍍忚檿鐞嗗柈鍏�銆�
銆�銆�4. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣滃崝(xi茅)铏曠悊鍣ㄤ互鍒嗘摂 CPU 鐨勮矤杓夛紝渚嬪澹撶府/瑙ｅ绺垨鍔犲瘑鎿嶄綔銆�
銆�銆�5. 瑕栭牷寤ｆ挱锛氳闋荤法纰艰В纰煎櫒鍜屽箑鍚屾闆昏矾鐨勮ō瑷�銆�
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XC7K410T-1FFG676C
銆�銆�XC7K325T-2FBG676C
銆�銆�XC7K160T-1FFG676C
