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XC7S50-1FTGB196C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Artix-7 绯诲垪 FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛変腑鐨勪竴鍝�銆傝┎鍣ㄤ欢鍩轰簬 28nm 宸ヨ棟鍒堕�狅紝鍏锋湁楂樺瘑搴﹂倧杓柈鍏�銆佽睈瀵岀殑 DSP 妯″鍜屽瓨鍎插櫒璩囨簮锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佸湒鍍忚檿鐞嗕互鍙婂伐妤�(y猫)鎺у埗绛夐牁(l菒ng)鍩�銆�
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鍨嬭櫉锛歑C7S50-1FTGB196C
銆�銆�绯诲垪锛欰rtix-7
銆�銆�鍝佺墝锛歑ilinx
銆�銆�FPGA閭忚集鍠厓鏁�(sh霉)閲忥細绱� 33,280 鍊�
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)閮ㄩ杻瀛橈紙闇�澶栫疆閰嶇疆鑺墖锛�
銆�銆�I/O寮曡叧鏁�(sh霉)锛�196
銆�銆�灏佽椤炲瀷锛欶TGB (Fine Pitch Thin Grid BGA)
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�宸ヨ棟绡�(ji茅)榛烇細28nm
銆�銆�鏍稿績闆诲锛�1.0V
銆�銆�I/O闆诲锛�1.8V, 2.5V, 3.3V
銆�銆�鏈�澶ч潨鎱�(t脿i)鍔熻�楋細1.5W
XC7S50-1FTGB196C 鎻愪緵浜嗛珮搴﹂潏娲荤殑鏋舵(g貌u)锛屾敮鎸佸閬� 50K 鐨勯倧杓柈鍏冿紙Logic Cells锛夛紝骞堕泦鎴愪簡璞愬瘜鐨勫姛鑳芥ā濉�銆傚畠鍖呮嫭澶氬�� Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屽彲鐢ㄤ簬瀵︾従(xi脿n)寰╅洔鐨勬暩(sh霉)鎿�(j霉)绶╂矕鍜屽瓨鍎茬鐞�銆傛澶�锛岃┎鑺墖閭勫収(n猫i)缃簡 DSP Slice锛屽彲浠ラ珮鏁堝煼(zh铆)琛屼箻娉曠疮鍔犻亱绠�锛屾豢瓒虫暩(sh霉)瀛椾俊铏熻檿鐞嗛渶姹傘��
銆�銆�姝� FPGA 鏀寔鏈�楂� 1.5Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屽苟鎻愪緵闈堟椿鐨勬檪閻樼鐞嗗伐鍏凤紙Clock Management Tiles, CMTs锛�锛岀敤浜庣敓鎴愮簿纰虹殑鏅傞悩淇¤櫉銆傚叾瑷�(sh猫)瑷堟祦绋嬪吋瀹� Vivado Design Suite锛屽厑瑷辩敤鎴堕�氶亷楂樺堡娆＄稖鍚堝拰 IP 鏍稿揩閫熸(g貌u)寤烘噳鐢ㄧ郴绲�(t菕ng)銆�
銆�銆�鐢变簬閲囩敤浜� UltraScale 鏋舵(g貌u)鎶�琛�(sh霉)锛岃┎鍣ㄤ欢鍏峰倷寮峰ぇ鐨勪簰閫ｈ兘鍔涘拰鍒嗗崁(q奴)鍎�(y艒u)鍖栬兘鍔�锛岄潪甯搁仼鍚堜腑灏忓瀷瑕�(gu墨)妯＄殑瑷�(sh猫)瑷堥爡鐩�銆�
XC7S50-1FTGB196C 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屽姗熷櫒瑕栬鐩告鍜岃闋诲垎鏋愯ō(sh猫)鍌欍��
銆�銆�2. 鏁�(sh霉)鎿�(j霉)閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂戒腑鐨勬暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌欙紝渚嬪瓒呰伈娉㈡巸鎻忓剙鍜� CT 閲嶅缓寮曟搸銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒跺櫒鍜岄亱鍕曟帶鍒剁郴绲�(t菕ng)銆�
銆�銆�5. 楂橀�熸暩(sh霉)鎿�(j霉)閲囬泦鍜屼俊铏熻檿鐞嗗钩鑷�銆�
銆�銆�6. 娓│娓噺鍎�鍣�锛屽寘鎷ず娉㈠櫒鍜屼换鎰忔尝褰㈢櫦(f膩)鐢熷櫒銆�
銆�銆�7. 鏁欒偛绉戠爺鐢ㄧ殑闆诲瓙宸ョ▼瀵﹂骞宠嚭銆�
銆�銆�8. 鍚勯鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)鍜岄倞绶ｈ▓绠楃瘈(ji茅)榛炪��
XC7S50T-1FTG256C
銆�銆�XC7S50-1CSG324C
