鍨嬭櫉(h脿o)锛歑C7S50-1FTGB196Q
銆�銆�閭忚集鍠�鍏冿��50,400
銆�銆�DSP Slice 鏁�(sh霉)閲忥細90
銆�銆�Block RAM锛�2.4MB
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細146
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�灏佽�濋�炲瀷锛欶TGB196
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�鏅�(sh铆)閻樼�＄悊鍠�鍏冿細Yes
銆�銆�PCIe 鏀�鎸侊細涓嶆敮鎸�
銆�銆�鏈�澶у伐浣滈牷鐜囷細550 MHz

XC7S50-1FTGB196Q 鐨勪富瑕佺壒鎬у寘鎷�锛�
銆�銆�1. 楂樻�ц兘鑸囦綆鍔熻�楃浉绲�(ji茅)鍚�锛岀壒鍒ラ仼鐢ㄤ簬灏�(du矛)鎴愭湰鏁忔劅浣嗛渶瑕佷竴瀹氳▓(j矛)绠楄兘鍔涚殑鍫�(ch菐ng)鏅�銆�
銆�銆�2. 鍏�(n猫i)缃�璞愬瘜鐨� DSP Slice锛屽彲浠ラ珮鏁堝��(sh铆)鐝�(xi脿n)婵炬尝鍣�銆丗FT 鍜屽叾浠栨暩(sh霉)瀛�(xu茅)閬�(y霉n)绠楀姛鑳�銆�
銆�銆�3. 鏀�鎸佸�氳矾宸�鍒嗚几鍏�/杓稿嚭妯�(bi膩o)婧�(zh菙n)锛屽�� LVDS銆丠STL 鍜� SSTL锛岄仼鐢ㄤ簬楂橀�熸帴鍙ｆ噳(y墨ng)鐢�銆�
銆�銆�4. 鎻愪緵闈堟椿鐨勫瓨鍎�(ch菙)鍣ㄦ灦妲�(g貌u)锛屽寘鍚� Block RAM 鍜屽垎甯冨紡 RAM锛岃兘澶犳豢瓒冲悇绋�鏁�(sh霉)鎿�(j霉)绶╁瓨闇�姹�銆�
銆�銆�5. 鍏�(n猫i)缃�鏅�(sh铆)閻樼�＄悊妯″�婏紙Clock Management Tile锛夛紝鍏佽ū鐢ㄦ埗閫�(j矛n)琛屾檪(sh铆)閻樺�嶉牷鎴栧垎闋绘搷浣�銆�
銆�銆�6. 鏀�鎸侀儴鍒嗛噸鏂伴厤缃�鍔熻兘锛屽彲浠ュ湪閬�(y霉n)琛屾湡闁撳嫊(d貌ng)鎱�(t脿i)鏇存柊 FPGA 鐨勬煇浜涘崁(q奴)鍩燂紝寰炶�屽劒(y艒u)鍖栬硣婧愬埄鐢ㄧ巼銆�
銆�銆�7. 灏佽�濈�� FTGB196锛屽叿鏈夎純灏忕殑澶栧舰灏哄��锛岄仼鍚堢┖闁撳彈闄愮殑瑷�(sh猫)瑷�(j矛)鐠�(hu谩n)澧冦��

XC7S50-1FTGB196Q 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栬ō(sh猫)鍌欎腑鐨勬帶鍒跺柈鍏冨拰閫氫俊鎺ュ彛銆�
銆�銆�2. 瑕栭牷鍜屽湒鍍忚檿鐞�锛屼緥濡傜洠(ji膩n)鎺�?c谩i)z鍍忛牠銆佽�栭牷绶ㄧ⒓鍣ㄧ瓑銆�
銆�銆�3. 閫氫俊绯荤当(t菕ng)涓�鐨勫熀甯惰檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻�銆�
銆�銆�4. 閱�(y墨)鐧傝ō(sh猫)鍌欎腑鐨勬暩(sh霉)鎿�(j霉)閲囬泦鍜屼俊铏�(h脿o)铏曠悊銆�
銆�銆�5. 娑堣不(f猫i)椤為浕瀛愮敘(ch菐n)鍝佷腑鐨勫祵鍏ュ紡鍦栧舰鍔犻�熷櫒銆�
銆�銆�6. 鐗╄伅(li谩n)缍�(w菐ng)缍�(w菐ng)闂�(gu膩n)鍜岄倞绶ｈ▓(j矛)绠楃瘈(ji茅)榛�(di菐n)涓�鐨勬��(sh霉)鎿�(j霉)铏曠悊骞宠嚭(t谩i)銆�
銆�銆�7. 娓�(c猫)瑭︽脯(c猫)閲�?j墨)x鍣ㄤ腑鐨勪俊铏�(h脿o)鐢熸垚鑸囧垎鏋愬柈鍏冦��

XC7S25-1FTGB196C
銆�銆�XC7A50T-1FGG484I
銆�銆�XC7S100-1FTGB196Q