鍨嬭櫉锛歑C7S6-1FTGB196C
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欰rtix-7
銆�銆�FPGA 瑕�(gu墨)妯★細6,900 鍊嬮倧杓�鍠�鍏�
銆�銆�閰嶇疆闁冨瓨锛氱劇鍏�(n猫i)缃�闁冨��
銆�銆�I/O 鏁�(sh霉)閲忥細146
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�灏佽�濆舰寮忥細FTGB196
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�鍔熻�楋細浣庡姛鑰楀劒(y艒u)鍖�
銆�銆�鏅傞悩闋荤巼锛氭渶楂樻敮鎸� 500MHz+
銆�銆�瀛樺劜璩囨簮锛氱磩 1.3Mb 鍒嗗竷寮� RAM 鍜屽�婄媭 RAM

XC7S6-1FTGB196C 鍏峰倷浠ヤ笅闂�(gu膩n)閸电壒鎬э細
銆�銆�1. 楂樺害闆嗘垚鐨勫彲绶ㄧ▼閭忚集璩囨簮锛屽寘鍚� CLB锛圕onfigurable Logic Block锛夊拰 DSP Slice锛岃兘澶�?q奴)宕縁(xi脿n)寰╅洔鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗗姛鑳�銆�
銆�銆�2. 鍏�(n猫i)缃�璞愬瘜鐨勫�栬ō(sh猫)鎺ュ彛鏀�鎸�锛屼緥濡� PCIe銆佸崈鍏嗕互澶�缍�(w菐ng) MAC 鍜� USB 鎺у埗鍣ㄧ瓑锛屾サ澶х啊鍖栦簡绯荤当(t菕ng)瑷�(sh猫)瑷堛��
銆�銆�3. 鏀�鎸侀儴鍒嗛噸閰嶇疆鎶�琛�(sh霉)锛屽厑瑷卞湪閬嬭�屾檪鍕曟��(t脿i)鏇存柊 FPGA 鐨勯儴鍒嗗崁(q奴)鍩熻�屼笉褰遍熆鍏朵粬鍔熻兘妯″�婄殑宸ヤ��銆�
銆�銆�4. 鎻愪緵纭�鏍� SERDES 妯″��锛屾敮鎸侀珮閬� 6.6Gbps 鐨勫偝杓搁�熺巼锛屾豢瓒抽珮閫熸暩(sh霉)鎿�(j霉)鍌宠几闇�姹傘��
銆�銆�5. 浣跨敤 Vivado Design Suite 鎴� ISE Design Tools 閫茶�岄枊鐧�(f膩)锛屽叿鍌欓珮鏁堢殑缍滃悎銆佷豢鐪熷拰甯冨眬甯冪窔宸ュ叿閺�銆�
銆�銆�6. 灏佽�濆舰寮� FTGB196 鎻愪緵绶婃箠鍨嬪紩鑵冲竷灞�锛屼究浜� PCB 瑷�(sh猫)瑷堣垏鍒堕��銆�

XC7S6-1FTGB196C 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷�鍕曞寲锛氬�� PLC 鎺у埗鍣�銆侀亱鍕曟帶鍒跺櫒鍜屾�熷櫒瑕栬�虹郴绲�(t菕ng)銆�
銆�銆�2. 閫氫俊瑷�(sh猫)鍌欙細鍖呮嫭灏忓瀷鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙�熶腑鐨勬��(sh霉)鎿�(j霉)鍖呰檿鐞�銆�
銆�銆�3. 閱�(y墨)鐧傝ō(sh猫)鍌欙細濡傝秴鑱叉尝鎴愬儚鍎�銆佸績闆诲湒瑷�(sh猫)鍌欎腑鐨勪俊铏熼噰闆嗚垏铏曠悊銆�
銆�銆�4. 姹借粖闆诲瓙锛欰DAS锛堥珮绱氶�曢�涜紨鍔╃郴绲�(t菕ng)锛夊拰杌婅級濞涙▊绯荤当(t菕ng)鐨勫湒鍍忚檿鐞�銆�
銆�銆�5. 娑堣不椤為浕瀛愮敘(ch菐n)鍝侊細瑕栭牷绶ㄨВ纰煎櫒銆佺劇浜烘�熼�涙帶绯荤当(t菕ng)绛�銆�
銆�銆�鍏堕潏娲荤殑鏋舵��(g貌u)鍜岄珮鎬ц兘琛ㄧ従(xi脿n)浣垮緱 XC7S6 鎴愮偤鐪惧�氬祵鍏ュ紡鎳�(y墨ng)鐢ㄧ殑鐞嗘兂瑙ｆ焙鏂规��銆�

XC7S5-1FTGB196C
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銆�銆�XC7A35T-1FGG484C