绯诲垪锛欰rtix-7
銆�銆�鍨嬭櫉(h脿o)锛歑C7S75-1FGGA484Q
銆�銆�FPGA 瀹归噺锛�75K 鍙�绶ㄧ▼閭忚集鍠�鍏�
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�I/O 鏁�(sh霉)閲忥細308
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master SPI
銆�銆�灏佽�濆舰寮忥細FGGA484
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�鏅�(sh铆)閻橀牷鐜囷細楂橀仈(d谩) 622 MHz
銆�銆�闆绘簮闆诲�擄細鏍稿績闆诲�撶偤 1.0V锛岃紨鍔╅浕澹撶偤 1.8V 鎴� 3.3V

XC7S75-1FGGA484Q 鎻愪緵浜嗚睈瀵岀殑鍔熻兘鐗规��锛屽寘鎷�浣嗕笉闄愪簬浠ヤ笅鍏�(n猫i)瀹癸細
銆�銆�1. 鍏�(n猫i)缃� DSP Slice锛屾敮鎸侀珮鏁堣檿鐞嗗京(f霉)闆滅畻娉曞拰淇¤櫉(h脿o)閬�(y霉n)绠椼��
銆�銆�2. 闆嗘垚浜� Block RAM 鍜� Distributed RAM锛岀敤浜庢暩(sh霉)鎿�(j霉)瀛樺劜(ch菙)鑸囩珐瀛樸��
銆�銆�3. 鏀�鎸侀珮閫熸敹鐧�(f膩)鍣�锛屽偝杓搁�熺巼鏈�楂樺彲閬�(d谩) 12.5Gbps锛堝湪鏇撮珮瑕�(gu墨)鏍煎瀷铏�(h脿o)涓�锛�銆�
銆�銆�4. 鎻愪緵澶氱ó纭�鏍告ā濉婂�� PCIe銆佸崈鍏嗕互澶�缍�(w菐ng)绛夋帴鍙ｏ紝渚夸簬绯荤当(t菕ng)闆嗘垚銆�
銆�銆�5. 鏀�鎸侀儴鍒嗛噸閰嶇疆鍔熻兘锛屽厑瑷卞��(d貌ng)鎱�(t脿i)瑾�(di脿o)鏁� FPGA 鐨勯倧杓�绲�(ji茅)妲�(g貌u)浠ラ仼鎳�(y墨ng)涓嶅悓浠诲嫏(w霉)闇�姹�銆�
銆�銆�6. 鎿佹湁浣庡姛鑰楁ā寮�锛岄仼鍚堥浕姹犱緵闆绘垨?q奴)未鑻勵灐鑸炬�拌��?y墨ng)鐢ㄥ牬(ch菐ng)鏅�銆�
銆�銆�7. 寮�(qi谩ng)澶х殑瑾�(di脿o)瑭﹀伐鍏烽張鏀�鎸�锛屼緥濡� Vivado Design Suite锛屾柟渚块枊鐧�(f膩)浜哄摗閫�(j矛n)琛岃ō(sh猫)瑷�(j矛)鍎�(y艒u)鍖栧拰椹�(y脿n)璀�銆�

XC7S75-1FGGA484Q 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬澶氬��(g猫)闋�(l菒ng)鍩燂紝鍏烽珨鍖呮嫭锛�
銆�銆�1. 宓屽叆寮忚�栬�虹郴绲�(t菕ng)锛屽�傛��(j墨)鍣ㄨ�栬��銆佸湒鍍忚檿鐞�銆佽�栭牷绶ㄧ⒓瑙ｇ⒓绛�銆�
銆�銆�2. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栨帶鍒讹紝渚嬪�� PLC 鎺у埗鍣�銆侀亱(y霉n)鍕�(d貌ng)鎺у埗鍣ㄧ瓑銆�
銆�銆�3. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂藉缓瑷�(sh猫)锛屾兜钃嬬劇绶氬熀绔�銆佽矾鐢卞櫒銆佷氦鎻涙��(j墨)绛夊姛鑳芥ā濉娿��
銆�銆�4. 閱�(y墨)鐧傛垚鍍忚ō(sh猫)鍌�锛屽�傝秴鑱叉尝鍎�鍣ㄣ�丆T 鎺冩弿鍎�鐨勬暩(sh霉)鎿�(j霉)铏曠悊閮ㄥ垎銆�
銆�銆�5. 娑堣不(f猫i)闆诲瓙闋�(l菒ng)鍩�锛屾瘮濡傞珮绔�椤�绀洪﹨(q奴)鍕�(d貌ng)銆侀煶闋昏檿鐞嗗櫒绛夌敘(ch菐n)鍝�銆�
銆�銆�6. 姹借粖闆诲瓙绯荤当(t菕ng)锛屾秹鍙� ADAS锛堥珮绱�(j铆)椐曢�涜紨鍔╃郴绲�(t菕ng)锛夌浉闂�(gu膩n)绲勪欢銆�

XC7S50T-1CSG324C, XC7A75T-FGGA484C