鏅傞枔锛�2025/5/28 23:30:27
闁辫畝锛�15
XC7V2000T-2FLG1925E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖銆傝┎绯诲垪鍣ㄤ欢閲囩敤鑷虹⿳闆� 28nm 宸ヨ棟鍒堕��锛屽叿鏈夐珮瀵嗗害閭忚集鍠厓銆佽睈瀵岀殑 DSP 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣ㄨ硣婧愶紝閬╁悎鐢ㄤ簬楂樻�ц兘瑷堢畻銆侀�氫俊鍩虹瑷柦銆佸湒鍍忚檿鐞嗗拰杌嶄簨鑸┖绛夐牁鍩�銆�
銆�銆�XC7V2000T 鏄� Virtex-7 绯诲垪涓殑涓�鍝�锛屽叾鍏�(n猫i)閮ㄥ寘鍚ぇ閲忕殑鍙法绋嬮倧杓硣婧�銆丷AM 濉娿�佷箻娉曞櫒浠ュ強鍚勭ó灏堢敤纭牳妯″銆傛澶�锛岃┎鍨嬭櫉鏀寔澶氱ó閰嶇疆妯″紡锛岃兘澶犳豢瓒充笉鍚岀殑瑷▓闇�姹�銆�
鍨嬭櫉锛歑C7V2000T-2FLG1925E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-7
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 200 钀��
銆�銆�Block RAM锛氱磩 32.6 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細4224 鍊�
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 940 鍊�
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂橀仈 13.1 Gbps
銆�銆�渚涢浕闆诲锛氬収(n猫i)鏍搁浕澹撶偤 1.0V锛孖/O 闆诲鑼冨湇鐐� 1.8V 鑷� 3.3V
銆�銆�灏佽椤炲瀷锛欶LG1925E
銆�銆�宸ヤ綔婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 95掳C锛夋垨宸ユキ(y猫)绱氾紙-40掳C 鑷� 100掳C锛�
XC7V2000T-2FLG1925E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘鏋舵(g貌u)锛氬熀浜� UltraScale 鏋舵(g貌u)锛屾彁渚涗簡鏇撮珮鐨勬�ц兘鍜屾洿浣庣殑鍔熻�椼��
銆�銆�2. 澶у閲忛倧杓硣婧愶細鍏峰倷楂橀仈 200 钀�嬮倧杓柈鍏�锛岄仼鍚堝京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗗拰鎺у埗閭忚集瑷▓銆�
銆�銆�3. 寮峰ぇ鐨� DSP 鍔熻兘锛氬収(n猫i)缃� 4224 鍊� DSP Slice锛屽彲浠ュ鐝�(xi脿n)楂樻晥鐨勬诞榛為亱绠楀拰婵炬尝绠楁硶銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鏀寔澶氳矾楂橀仈 13.1 Gbps 鐨勯珮閫熶覆琛屾帴鍙�锛岄仼鐢ㄤ簬閫氫俊绯荤当(t菕ng)涓殑鏁�(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�5. 澶氭ǎ鍖栫殑瀛樺劜璩囨簮锛氭彁渚涜睈瀵岀殑 Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屼究浜庡鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)鎿�(j霉)绶╁瓨鍔熻兘銆�
銆�銆�6. 鍙潬鎬у寮凤細鏀寔閮ㄥ垎鍕曟厠(t脿i)閲嶆(g貌u)鎶�琛�(sh霉)锛岃兘澶犲湪閬嬭鏅傛洿鏂拌ō瑷堬紝鎻愬崌闈堟椿鎬�銆�
銆�銆�7. 寤ｆ硾鐨� I/O 妯欐簴鏀寔锛氬吋瀹瑰绋婧栫殑 I/O 鍗�(xi茅)璀帮紝鏂逛究鑸囧閮ㄨō鍌欓�ｆ帴銆�
銆�銆�8. 鍏�(n猫i)缃‖鏍� IP锛氬 PCIe Gen3銆�10Gb Ethernet 绛�锛岀啊鍖栦簡绯荤当(t菕ng)闆嗘垚閬庣▼銆�
銆�銆�9. 瀹屽杽鐨勮ō瑷堝伐鍏锋敮鎸侊細閫氶亷 Vivado Design Suite 鎻愪緵鍏ㄩ潰鐨勮ō瑷堝劒(y艒u)鍖栧拰瑾�(di脿o)瑭﹀姛鑳�銆�
XC7V2000T-2FLG1925E 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊瑷倷锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒銆佷氦鎻涙绛�锛岀敤浜庡崝(xi茅)璀拌檿鐞�銆佹祦閲忕鐞嗗拰鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鐧�(f膩)銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績锛氬湪鏈嶅嫏鍣ㄥ姞閫熷崱涓娇鐢紝鍩�(zh铆)琛屾鍣ㄥ缈掓帹鐞嗐�佸姞瀵嗚В瀵嗙瓑浠诲嫏銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬瓒呰伈娉��丆T 鎺冩弿鍎�绛夎ō鍌欎腑鐨勫湒鍍忚檿鐞嗗拰瀵︽檪鍒嗘瀽銆�
銆�銆�4. 杌嶄簨鑸囪埅绌鸿埅澶╋細婊胯冻闆烽仈銆佽(w猫i)鏄熼�氫俊鍙婂皫鑸郴绲�(t菕ng)鐨勯珮鎬ц兘瑕佹眰銆�
銆�銆�5. 瑕栭牷寤ｆ挱锛氭敮鎸侀珮娓呰闋荤法纰艰В纰煎拰鍦栧儚澧炲挤銆�
銆�銆�6. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)瀵︽檪鎺у埗鍜屽京闆滅畻娉曡檿鐞�銆�
XC7V2000T-3FLG1925E
銆�銆�XC7VX690T-2FFG1930E
銆�銆�XC7VX690T-3FFG1930E
