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XC7V2000T-2FLG1925I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏熴�傝┎绯诲垪 FPGA 灏堢偤楂樻�ц兘瑷堢畻銆侀�氫俊銆佸唬鎾互鍙婂伐妤�(y猫)鎳夌敤瑷▓锛屾彁渚涗簡璞愬瘜鐨勯倧杓硣婧�銆佹暩瀛椾俊铏熻檿鐞� (DSP) 妯″鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣紝閬╃敤浜庡京闆滅殑绯荤当(t菕ng)绱氶泦鎴愰渶姹�銆�
銆�銆�Virtex-7 绯诲垪閲囩敤浜嗚嚭绌嶉浕 (TSMC) 鐨� 28nm 鍒剁▼宸ヨ棟锛屽叿鍌欓珮瀵嗗害閭忚集鍠厓銆佸ぇ瀹归噺 Block RAM 鍜屽垎甯冨紡 RAM锛屾敮鎸佸绋厤缃ā寮忓強闈堟椿鐨勬檪閻樼鐞�銆傛澶�锛岃┎鑺墖閭勯泦鎴愪簡 PCIe 纭牳妯″锛屾柟渚跨敤鎴跺揩閫熷鐝捐垏涓绘绯荤当(t菕ng)鐨勯�ｆ帴銆�
鍨嬭櫉锛歑C7V2000T-2
銆�銆�灏佽锛欶LG1925I
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閭忚集鍠厓鏁搁噺锛氱磩 2,036,000
銆�銆�Block RAM 瀹归噺锛�12.4Mb
銆�銆�DSP Slice 鏁搁噺锛�2,160
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster/Slave Serial銆丮aster/Slave Parallel
銆�銆�I/O Bank 鏁搁噺锛�24
銆�銆�鏈�澶х敤鎴� I/O 鏁搁噺锛�1,152
銆�銆�楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄦ暩閲忥細32
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛�1Mbps 鑷� 13.1Gbps
銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 1.0V锛岃紨鍔╅浕澹� 1.8V锛孖/O 闆诲 1.8V 鎴� 3.3V
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銆�銆�1. 楂樻�ц兘閭忚集绲愭锛氬熀浜� UltraScale 鏋舵鐨勫彲绶ㄧ▼閭忚集鍠厓鍏佽ū鐢ㄦ埗瀵︾従寰╅洔鐨勬暩瀛楅浕璺紝鍚屾檪鎻愪緵鏇撮珮鐨勮硣婧愬埄鐢ㄧ巼鍜岄亱琛岄�熷害銆�
銆�銆�2. 寮峰ぇ鐨� DSP 鍔熻兘锛氬収宓岀殑 DSP Slice 鏀寔楂樻晥鐨勬暩鎿氶亱绠楋紝寤ｆ硾鎳夌敤浜庡湒鍍忚檿鐞�銆佽闋荤法纰艰В纰煎拰閫氫俊淇¤櫉铏曠悊绛夐牁鍩熴��
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銆�銆�5. 闈堟椿鐨勬檪閻樼鐞嗭細鍏х疆 PLL 鍜� MMCM 妯″锛屾彁渚涚簿婧栫殑鏅傞悩鍒嗛厤鍜岄牷鐜囩稖鍚堝姛鑳�銆�
銆�銆�6. 澧炲挤鐨勫畨鍏ㄦ�э細鏀寔 AES 鍔犲瘑鍜� HMAC 瑾嶈瓑锛屼繚璀风敤鎴惰ō瑷堢殑鐭ヨ瓨鐢㈡瑠銆�
XC7V2000T-2FLG1925I 鍦ㄥ鍊嬮牁鍩熶腑閮芥湁寤ｆ硾鎳夌敤锛屽寘鎷絾涓嶉檺浜庯細
銆�銆�1. 楂樻�ц兘瑷堢畻锛氬彲鐢ㄤ簬鍔犻�熺瀛歌▓绠�銆佹鍣ㄥ缈掔畻娉曞拰鏁告摎鍒嗘瀽銆�
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銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鏀寔寰╅洔鐨勬帶鍒堕倧杓拰楂橀�熸暩鎿氶噰闆�銆�
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銆�銆�6. 姹借粖闆诲瓙锛氬湪鑷嫊椐曢杓斿姪绯荤当(t菕ng)涓煼(zh铆)琛岀洰妯欒瓨鍒ュ拰璺緫瑕�(gu墨)鍔冧换鍕�銆�
XC7VX690T-2FLG1925I
銆�銆�XC7VX415T-2FLG1925I
銆�銆�XC7VX550T-2FLG1925I
