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XC7V585T-2FF1761I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖锛岃┎绯诲垪鑺墖閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛屽叿鏈夐珮瀵嗗害閭忚集鍠厓銆佽睈瀵岀殑 DSP Slice 鍜屽ぇ瀹归噺鐨勫祵鍏ュ紡瀛樺劜鍣�銆傞�欐 FPGA 闈炲父閬╁悎楂樻�ц兘瑷堢畻銆侀�氫俊绯荤当(t菕ng)銆佷俊铏熻檿鐞嗗拰寰╅洔宓屽叆寮忔噳鐢ㄧ瓑鍫存櫙銆傚畠鏀寔楂橀�熶覆琛屾敹鐧�(f膩)鍣紙GTX/GTH锛夛紝鑳藉瀵︾従(xi脿n)楂橀仈 6.6 Gbps 鎴栨洿楂樼殑鏁�(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�姝ゅ锛孹C7V585T-2FF1761I 閭勬彁渚涢潏娲荤殑 I/O 妯欐簴鍏煎鎬т互鍙婂挤澶х殑鏅傞悩绠＄悊鍔熻兘锛岄仼鐢ㄤ簬闇�瑕侀珮搴﹂泦鎴愬拰浣庡姛鑰楃殑瑷▓銆�
鍨嬭櫉锛歑C7V585T
銆�銆�灏佽锛欶F1761
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�閭忚集鍠厓鏁�(sh霉)锛氱磩 585,000
銆�銆�Block RAM锛�34.7 Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2,800
銆�銆�閰嶇疆妯″紡锛歋electMAP銆丮aster SPI銆丼lave SPI銆丮aster BPI銆丼lave BPI
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1,240
銆�銆�宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +85掳C锛�
銆�銆�鍒剁▼宸ヨ棟锛�28nm
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銆�銆�2. 鍏х疆楂橀�熸敹鐧�(f膩)鍣細闆嗘垚 GTX 鍜� GTH 鏀剁櫦(f膩)鍣ㄦā濉�锛屾敮鎸佸緸 600 Mbps 鍒� 6.6 Gbps 鐨勫绋�熺巼鑼冨湇銆�
銆�銆�3. 寮峰ぇ鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涳細閰嶅倷 2,800 鍊� DSP Slice锛岀敤浜庨珮鏁堝鐝�(xi脿n)娴粸閬嬬畻銆佹烤娉㈠拰鍏朵粬寰╅洔绠楁硶銆�
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銆�銆�6. 鍙摯灞曟�у挤锛氶�氶亷澶氶 FPGA 鐨勫爢鐤婁簰鑱�(li谩n)鎶�琛擄紙Stacked Silicon Interconnect锛�锛屽彲浠ラ�蹭竴姝ユ摯灞曠郴绲�(t菕ng)瀹归噺鍜屾�ц兘銆�
銆�銆�7. 瀹夊叏鐗规�э細鎻愪緵 AES 鍔犲瘑銆丼HA-256 瑾嶈瓑鍙� Bitstream 绨藉悕椹楄瓑绛夊姛鑳斤紝淇濋殰鐭ヨ瓨鐢㈡瑠鍜岃ō瑷堝畨鍏�銆�
XC7V585T-2FF1761I 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鍩虹珯铏曠悊鍠厓銆佺恫绲′氦鎻涜ō鍌欏拰璺敱鍣�銆�
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鍖呮嫭瀵︽檪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮蜂互鍙婅▓绠楁瑕栬鐩搁棞浠诲嫏銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹細瀵︾従(xi脿n)寰╅洔鐨勯亱鍕曟帶鍒剁畻娉曟垨鍒嗗竷寮忔帶鍒剁郴绲�(t菕ng)銆�
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銆�銆�5. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬鏁�(sh霉)鎿�(j霉)搴煡瑭㈠姞閫熴�佸姞瀵嗚В瀵嗘湇鍕欑瓑銆�
銆�銆�6. 娓│娓噺鍎�鍣細濡傞珮鎬ц兘绀烘尝鍣ㄣ�佸崝(xi茅)璀板垎鏋愬剙绛夎ō鍌欎腑鐨勬牳蹇冭檿鐞嗗柈鍏�銆�
XC7V585T-3FF1761I
銆�銆�XC7VX550T-2FFG1761I
銆�銆�XC7VX690T-2FFG1761I
