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銆€銆€Virtex-7 绯诲垪閲囩敤鑷虹⿳闆� 28nm 鍒剁▼宸ヨ棟鍒堕€�锛屽叿鏈変綆鍔熻€楀拰楂樻€ц兘鐨勭壒榛�銆傛鍨嬭櫉涓殑鈥�585鈥濊〃绀哄叾閭忚集鍠厓鐨勬暩(sh霉)閲忕磩鐐� 58.5 钀€嬶紝閬╁悎涓埌澶ц(gu墨)妯＄殑鏁�(sh霉)瀛楅浕璺鐝�(xi脿n)銆�

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鍨嬭櫉锛歑C7V585T-3FFG1761C
銆€銆€灏佽褰㈠紡锛欶FG1761
銆€銆€閭忚集鍠厓鏁�(sh霉)锛�585K
銆€銆€鍒剁▼宸ヨ棟锛�28nm
銆€銆€閰嶇疆妯″紡锛歋electMAP, Master SPI, Slave SPI
銆€銆€鍏�(n猫i)閮ㄥ瓨鍎插櫒锛�2340KB
銆€銆€DSP Slice 鏁�(sh霉)閲忥細2880
銆€銆€鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲忥細48
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€I/O 閵€琛屾暩(sh霉)閲忥細48
銆€銆€渚涢浕闆诲锛�1.0V 鏍稿績闆诲 / 1.8V 杓斿姪闆诲

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XC7V585T-3FFG1761C 鎻愪緵鍗撹秺鐨勬€ц兘鑸囬潏娲绘€э紝鍏堕棞(gu膩n)閸电壒鎬у寘鎷細
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