鏅傞枔锛�2025/5/23 7:35:29
闁辫畝锛�15
XC7VH870T-1FLG1932 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪楂樼 FPGA 鑺墖锛岃┎绯诲垪浠ラ珮鎬ц兘銆侀珮閭忚集瀵嗗害鍜岄潏娲荤殑鏋舵瑷▓鑰岃仦鍚嶃�傞�欐 FPGA 閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛岄仼鐢ㄤ簬寰╅洔绠楁硶铏曠悊銆佷俊铏熻檿鐞�銆佸湒鍍忚檿鐞嗕互鍙婇珮鎬ц兘瑷堢畻绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�瀹冩敮鎸佸绋珮閫熸帴鍙ｅ崝(xi茅)璀�锛屽苟鍏峰倷璞愬瘜鐨勫収閮ㄨ硣婧愶紙濡� DSP Slice 鍜� Block RAM锛�锛岃兘澶犳豢瓒冲緸閫氫俊鍒拌埅绌鸿埅澶╃瓑澶氬�嬭妤�(y猫)鐨勫毚鑻涢渶姹傘��
鍨嬭櫉锛歑C7VH870T-1FLG1932
銆�銆�灏佽锛�1932-Pin FCBGA
銆�銆�宸ヨ棟鍒剁▼锛�28nm
銆�銆�閰嶇疆妯″紡锛歁aster SPI, Slave Serial/Parallel, Boundary Scan
銆�銆�I/O 鏁�(sh霉)閲忥細1456
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細873600
銆�銆�Block RAM 瀹归噺锛�48.1Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細3520
銆�銆�鏈�澶у伐浣滈牷鐜囷細675MHz
銆�銆�鍔熻�楄寖鍦嶏細鏍规摎(j霉)浣跨敤鎯呮硜鍕曟厠(t脿i)瑾挎暣
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XC7VH870T-1FLG1932 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囬潏娲绘��锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂橀仈 873600 鍊嬮倧杓柈鍏�锛屾敮鎸佸ぇ瑕�(gu墨)妯℃暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 鍏х疆 3520 鍊� DSP Slice锛岀敤浜庨珮鏁堢殑娴粸閬嬬畻鍜屼俊铏熻檿鐞�銆�
銆�銆�3. 鎿佹湁 48.1Mb 鐨勫垎甯冨紡 Block RAM锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜屽瓨鍎�銆�
銆�銆�4. 鏀寔楂橀仈 675MHz 鐨勯亱琛岄牷鐜�锛岀⒑淇濆鏅傝檿鐞嗚兘鍔�銆�
銆�銆�5. 閰嶅倷澶氬�嬮珮閫熶覆琛屾敹鐧�(f膩)鍣� (GTH/GTX)锛屽偝杓搁�熺巼鏈�楂樺彲閬� 13.1Gbps锛岄仼鐢ㄤ簬鍏夌簴閫氫俊鍜屽叾浠栭珮閫熸噳鐢ㄥ牬鏅�銆�
銆�銆�6. 鎻愪緵闈堟椿鐨勬檪閻樼鐞嗗姛鑳�锛屽寘鎷� PLL 鍜� MMCM 妯″锛屽彲鐢熸垚绮剧⒑鐨勬檪閻樹俊铏�銆�
銆�銆�7. 闆嗘垚浜嗗ぇ瀹归噺鐢ㄦ埗闁冨瓨 (FPGA Configuration Flash) 鍜屽绋瑷帴鍙ｆ帶鍒跺櫒锛岀啊鍖栫郴绲�(t菕ng)瑷▓銆�
XC7VH870T-1FLG1932 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 楂樻�ц兘瑷堢畻 (HPC)锛氬彲鐢ㄤ簬鍔犻�熺瀛歌▓绠椼�侀噾铻嶅缓妯＄瓑浠诲嫏銆�
銆�銆�2. 閫氫俊瑷倷锛氬寘鎷熀绔�銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏍稿績淇¤櫉铏曠悊閮ㄥ垎銆�
銆�銆�3. 鍦栧儚鑸囪闋昏檿鐞嗭細瀵︾従(xi脿n)瀵︽檪瑕栭牷绶ㄨВ纰�銆佸寮峰強鍒嗘瀽绛夊姛鑳�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鎺у埗寰╅洔姗熸瑷倷骞跺劒(y艒u)鍖栫敓鐢�(ch菐n)娴佺▼銆�
銆�銆�5. 閱�(y墨)鐧傝ō鍌欙細渚嬪瓒呰伈娉㈡垚鍍忓剙鍜屾牳纾佸叡鎸巸鎻忓剙鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�銆�
銆�銆�6. 鑸┖鑸ぉ锛氬皫鑸郴绲�(t菕ng)銆佽(w猫i)鏄熻級鑽风瓑闋樺煙闇�瑕侀珮搴﹀彲闈犳�х殑鍫村悎銆�
銆�銆�7. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣滄湇鍕欏櫒鍔犻�熷崱鐨勬牳蹇冪祫浠�锛屾彁鍗囨暩(sh霉)鎿�(j霉)鍚炲悙閲忓拰铏曠悊鏁堢巼銆�
XC7VH580T-1FFG1157I
銆�銆�XC7VH580T-1FFG1157C
銆�銆�XC7VH870T-2FFG1157I
銆�銆�XC7VH870T-2FFG1157C
