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XC7VH870T-L2FLG1932E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鑺墖涓昏闈㈠悜楂樻�ц兘瑷堢畻銆侀�氫俊鍩虹瑷柦銆佽埅绌鸿埅澶╁拰鍦嬮槻绛夐牁鍩�銆俋C7VH870T 鍩轰簬 28nm 宸ヨ棟鍒剁▼锛岄泦鎴愪簡璞愬瘜鐨勯倧杓硣婧�銆侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄣ�丏SP 妯″浠ュ強澶у閲忕殑宓屽叆寮忓瓨鍎插櫒銆�
銆�銆�姝よ姱鐗囧叿鏈夐珮闆嗘垚搴﹀拰闈堟椿鎬�锛岃兘澶犳豢瓒冲京闆滆ō瑷堢殑闇�姹�锛屼緥濡傞珮绔俊铏熻檿鐞嗐�佸湒鍍忚檿鐞嗕互鍙婃暩鎿氶�氫俊绛夋噳鐢�銆�
鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�绯诲垪锛歏irtex-7
銆�銆�灏佽褰㈠紡锛欶LG1932E
銆�銆�閫熷害绛夌礆锛歀2
銆�銆�閭忚集鍠厓鏁搁噺锛�870K
銆�銆�RAM 瀹归噺锛�54Mb
銆�銆�DSP Slice 鏁搁噺锛�2160
銆�銆�I/O 鏁搁噺锛�1046
銆�銆�閰嶇疆妯″紡锛歋electMAP 鍜� Master SPI
銆�銆�宸ヤ綔闆诲锛�0.95V 鏍稿績闆诲 / 1.0V I/O 闆诲
銆�銆�鏈�澶у伐浣滄韩搴﹁寖鍦嶏細-40掳C 鑷� +100掳C
XC7VH870T-L2FLG1932E 鎻愪緵浜嗗绋珮鎬ц兘鐗规��銆傞鍏堬紝瀹冨叿鍌欏閬� 870K 鐨勯倧杓柈鍏�锛屽彲浠ュ鐝惧京闆滅殑鏁稿瓧闆昏矾瑷▓銆傚叾娆�锛屽収缃湁 2160 鍊� DSP Slice锛岄仼鍚堝畬鎴愬瘑闆嗗瀷鏁稿閬嬬畻浠诲嫏锛屽婵炬尝銆丗FT 鍜岀煩闄ｉ亱绠楃瓑銆傛澶�锛屽叾鏀寔楂橀仈 28.05 Gbps 鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣�锛岀⒑淇濆湪鏁告摎鍌宠几鏂归潰鎿佹湁妤甸珮鐨勫付瀵兘鍔�銆�
銆�銆�瑭茶姱鐗囬倓闆嗘垚浜嗚睈瀵岀殑澶栬ō鎺ュ彛閬搁爡锛屽寘鎷� PCIe Gen3銆佺櫨鍏�/鍗冨厗浠ュお缍� MAC 鍜屼笁?锛熷垈鐮撮灟瑁櫸磋嫞顥嶬锛屽緸鑰岀啊鍖栦簡绯荤当(t菕ng)绱氳ō瑷堥亷绋�銆傚悓鏅�锛孹ilinx 鐨� Vivado 瑷▓濂椾欢鐐洪枊鐧�(f膩)鑰呮彁渚涗簡寮峰ぇ鐨勫伐鍏锋敮鎸�锛屽公鍔╀粬鍊戝揩閫熼枊鐧�(f膩)骞跺劒(y艒u)鍖栧熀浜� XC7VH870T 鐨勯爡鐩��
XC7VH870T-L2FLG1932E 涓昏鎳夌敤浜庡皪鎬ц兘瑕佹眰杓冮珮鐨勯牁鍩燂紝鍖呮嫭浣嗕笉闄愪簬锛�
銆�銆�1. 楂樼閫氫俊瑷倷锛屼緥濡傝矾鐢卞櫒銆佷氦鎻涙鍜屽熀绔�;
銆�銆�2. 瑕栭牷鑸囧湒鍍忚檿鐞嗚ō鍌�锛屽楂樻竻鏀濆儚姗熷拰閱�(y墨)鐧傛垚鍍忕郴绲�(t菕ng);
銆�銆�3. 鏁告摎涓績鍔犻�熷崱锛岀敤浜庢彁鍗囨湇鍕欏櫒瑷堢畻鏁堢巼;
銆�銆�4. 鑸┖鑸ぉ鍜屽湅闃查牁鍩熺殑闆烽仈绯荤当(t菕ng)銆佸皫鑸ō鍌欏強琛�(w猫i)鏄熻級鑽锋帶鍒�;
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栧拰姗熷櫒浜烘妧琛撲腑鐨勫鏅傛帶鍒跺柈鍏�銆�
銆�銆�閫欎簺鎳夌敤鍫存櫙鍏呭垎鍒╃敤浜嗚┎ FPGA 寮峰ぇ鐨勫苟琛岃檿鐞嗚兘鍔涘拰闈堟椿鐨勫彲绶ㄧ▼鎬�銆�
XC7VH580T-2FFG1157I, XC7VH580T-2FFG1157E, XC7VH580T-2FLG1932E
