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闁辫畝锛�35
XC7VX1140T-2FL1926I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖锛岃┎绯诲垪浠ラ珮鎬ц兘銆侀珮閭忚集瀵嗗害鍜屼綆鍔熻�楃偤鐗归粸锛岄仼鐢ㄤ簬楂樼鏁�(sh霉)瀛椾俊铏熻檿鐞� (DSP)銆佸湒鍍忚檿鐞�銆侀�氫俊绯荤当(t菕ng)瑷▓浠ュ強鍏朵粬闇�瑕侀珮搴﹀苟琛岃▓绠楄兘鍔涚殑鎳夌敤鍫存櫙銆傛鍨嬭櫉鐨� XC7VX1140T 鐗瑰垾閬╁悎瑕佹眰寰╅洔绠楁硶瀵︾従(xi脿n)鎴栧ぇ瑕�(gu墨)妯℃暩(sh霉)鎿�(j霉)鍚炲悙閲忕殑鍫村悎銆�
銆�銆�Virtex-7 绯诲垪閲囩敤 28nm 鍒剁▼宸ヨ棟鍒堕��锛屾彁渚涗簡璞愬瘜鐨勭‖浠惰硣婧愶紝鍖呮嫭鍙法绋嬮倧杓柈鍏�銆佸瓨鍎插櫒濉�銆佹暩(sh霉)瀛椾俊铏熻檿鐞嗗櫒 (DSP Slice) 鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣ㄧ瓑銆�
鍣ㄤ欢鍨嬭櫉锛歑C7VX1140T
銆�銆�灏佽椤炲瀷锛欶LGA1926
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 1,140,000
銆�銆�RAM 瀹归噺锛氱磩 6,552 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 2,280
銆�銆�閰嶇疆妯″紡锛歋lave Serial / Master SelectMAP / Boundary Scan
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶氭敮鎸� 864 鍊嬬敤鎴� I/O
XC7VX1140T-2FL1926I 鎻愪緵浜嗗挤澶х殑鍔熻兘鍜岄潏娲绘�э紝鍏朵富瑕佺壒鎬у涓嬶細
銆�銆�1. 楂樺瘑搴﹀彲绶ㄧ▼閭忚集锛氭鑺墖鍖呭惈澶х磩 114 钀�嬮倧杓柈鍏�锛岃兘澶犳豢瓒冲京闆滅殑鏁�(sh霉)瀛楅浕璺ō瑷堥渶姹傘��
銆�銆�2. 鍏�(n猫i)缃� DSP 妯″锛氭彁渚涘閬� 2,280 鍊� DSP Slice锛岀敤浜庨珮鏁堝鐝�(xi脿n)涔樻硶绱姞绛夐亱绠楋紝鐗瑰垾閬╁悎鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�銆�
銆�銆�3. 澶у閲忓祵鍏ュ紡瀛樺劜鍣細鍏峰倷绺借▓绱� 6.5 Mb 鐨� Block RAM 鍜� Distributed RAM锛屾敮鎸佸绋暩(sh霉)鎿�(j霉)绶╂矕鍜岀珐瀛樻搷浣�銆�
銆�銆�4. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細闆嗘垚楂橀仈 24 鍊� GTH 鏀剁櫦(f膩)鍣�锛屾敮鎸侀�熺巼鑼冨湇寰炲咕鐧� Mbps 鍒版渶楂� 6.6 Gbps锛屽彲鐢ㄤ簬鍏夌簴閫氫俊銆丳CIe 鎺ュ彛绛夋噳鐢�銆�
銆�銆�5. 鍔熻�楀劒(y艒u)鍖栵細閫氶亷鍕曟厠(t脿i)闆诲瑾�(di脿o)绡�(ji茅)鍜屾檪閻橀杸鎺ф妧琛撻檷浣庨亱琛屽姛鑰楋紝鍚屾檪鎻愪緵闈堟椿鐨勯浕婧愮鐞嗛伕闋�銆�
銆�銆�6. 寤ｆ硾鐨勬帴鍙ｆ敮鎸侊細鏀寔 DDR3/DDR2/LPDDR 瀛樺劜鍣ㄦ帴鍙ｏ紝浠ュ強 PCIe Gen2銆丼ATA 鍜屽崈鍏嗕互澶恫(w菐ng)绛夊绋崝(xi茅)璀般��
XC7VX1140T-2FL1926I 甯歌鐨勬噳鐢ㄩ牁鍩熷寘鎷絾涓嶉檺浜庝互涓嬫柟闈細
銆�銆�1. 楂樼閫氫俊瑷倷锛氬鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑鏍稿績淇¤櫉铏曠悊閮ㄥ垎銆�
銆�銆�2. 閱�(y墨)鐧傛垚鍍忥細鍦ㄨ秴鑱叉尝瑷倷銆丆T 鎺冩弿鍎�鍜� MRI 绯荤当(t菕ng)涓矤璨鏅傚湒鍍忕敓鎴愬拰铏曠悊銆�
銆�銆�3. 瑕栭牷铏曠悊锛氭噳鐢ㄤ簬瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佹祦濯掗珨鍌宠几鍙婂皥妤�(y猫)鍦栧舰娓叉煋銆�
銆�銆�4. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬鍔犻�熸悳绱㈢畻娉�銆佹鍣ㄥ缈掓帹鐞嗙瓑浠诲嫏銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栵細浣滅偤鎺у埗绯荤当(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒锛岃檿鐞嗗偝鎰熷櫒杓稿叆鍜屽煼(zh铆)琛屾帶鍒跺懡浠ゃ��
銆�銆�6. 鑸┖鑸ぉ鑸囧湅闃诧細閬╃敤浜庤(w猫i)鏄熼�氫俊銆侀浄閬斾俊铏熻檿鐞嗗強鍏朵粬闂滈嵉浠诲嫏鐠�(hu谩n)澧�銆�
XC7VX1140T-3FLG1926C, XC7VX1140T-3FLG1926I
