鍨嬭櫉锛歑C7VX330T-2FFV1761I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex-7
銆�銆�灏佽�濓細FFV1761
銆�銆�I/O 鏁�(sh霉)閲忥細1500+
銆�銆�閰嶇疆妯″紡锛歋lave Serial, Master SPI, SelectMAP
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�鏍稿績闆诲�擄��1.0V
銆�銆�澶栬ō(sh猫)闆诲�擄��1.8V/2.5V/3.3V
銆�銆�FPGA 瀹归噺锛�330K Logic Cells
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2160
銆�銆�Block RAM锛氱磩 20MB
銆�銆�鍏�(n猫i)閮� Flash锛氱劇锛堥渶澶栫疆閰嶇疆鑺�鐗囷��
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬� 13.1 Gbps

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銆�銆�1. 楂橀倧杓�瀵嗗害锛氬叿鍌� 330K 鍙�绶ㄧ▼閭忚集鍠�鍏�锛屾豢瓒冲京(f霉)闆滅畻娉曞�︾��(xi脿n)鐨勯渶姹傘��
銆�銆�2. 楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛氭敮鎸侀珮閬� 13.1Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鐢ㄤ簬楂橀�熸帴鍙ｈō(sh猫)瑷堬紝濡� PCIe Gen3銆丆PRI銆丼RIO 绛�銆�
銆�銆�3. 澶ц��(gu墨)妯″瓨鍎茶硣婧愶細鍖呭惈绱� 20MB 鐨� Block RAM 鍜� 2160 鍊� DSP Slice锛屽彲鏀�鎸佸ぇ瑕�(gu墨)妯℃暩(sh霉)鎿�(j霉)绶╁瓨鍜岄珮鎬ц兘鏁�(sh霉)瀛椾俊铏熻檿鐞�銆�
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銆�銆�5. 寤ｆ硾鐨勬噳(y墨ng)鐢ㄦ敮鎸侊細閫氶亷纭�鏍� IP锛堜緥濡� PCIe銆両nterlaken 绛夛級鍜岃粺鏍告灦妲�(g貌u)锛堝�� MicroBlaze锛�锛岃兘澶犲揩閫熸��(g貌u)寤哄京(f霉)闆滅殑宓屽叆寮忕郴绲�(t菕ng)銆�
銆�銆�6. 浣庡姛鑰楀劒(y艒u)鍖栵細閲囩敤 28nm HPT 宸ヨ棟锛屽湪淇濊瓑鎬ц兘鐨勫悓鏅傞’钁楅檷浣庡姛鑰楁按骞�銆�
銆�銆�7. 寮峰ぇ鐨勯枊鐧�(f膩)宸ュ叿閺堬細閰嶅悎 Vivado Design Suite锛屽彲浠ュ�︾��(xi脿n)楂樻晥鐨� RTL 瑷�(sh猫)瑷�銆佺稖鍚堛�佸竷灞�甯冪窔鍙婇�楄瓑娴佺��銆�

瑭插瀷铏熷唬娉涙噳(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂斤細鍖呮嫭鐒＄窔鍩虹珯銆佸厜绾栧偝杓歌ō(sh猫)鍌欏拰缍�(w菐ng)绲�(lu貌)浜ゆ彌姗熶腑鐨勫崝(xi茅)璀拌綁(zhu菐n)鎻�銆佹暩(sh霉)鎿�(j霉)鍖呰檿鐞嗙瓑鍔熻兘銆�
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銆�銆�3. 宸ユキ(y猫)鑷�鍕曞寲锛氱敤浣滈亱鍕曟帶鍒�銆佹�熷櫒浜鸿�栬�烘垨鍒嗗竷寮忔帶鍒剁郴绲�(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒銆�
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XC7VX330T-3FFV1761I
銆�銆�XC7VX415T-2FFV1761I
銆�銆�XC7VX415T-3FFV1761I