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XC7VX415T-2FFG1157E 鏄� Xilinx锛堣辰闈堟�濓級鍏徃鎺ㄥ嚭鐨� Virtex-7 绯诲垪 FPGA 鑺墖锛屽爆浜庨珮鎬ц兘銆侀珮瀵嗗害 FPGA 鐢�(ch菐n)鍝佺窔銆傝┎绯诲垪鑺墖閲囩敤鑷虹⿳闆� 28nm 宸ヨ棟鍒堕�狅紝鏀寔楂橀仈 2.1Gb 鐨勭墖涓婂瓨鍎插櫒瀹归噺锛屽苟鎻愪緵璞愬瘜鐨� DSP Slice 鍜屽彲绶ㄧ▼閭忚集璩囨簮銆傛澶�锛屽畠閭勯泦鎴愪簡楂橀�熶覆琛屾敹鐧�(f膩)鍣�锛岃兘澶犲鐝�(xi脿n)楂橀仈 13.1Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�Virtex-7 绯诲垪 FPGA 寤ｆ硾鎳夌敤浜庨�氫俊鍩虹瑷柦銆佽埅绌鸿埅澶╄垏鍦嬮槻銆佸唬鎾闋昏檿鐞�銆侀啱(y墨)鐧傛垚鍍忎互鍙婇珮鎬ц兘瑷堢畻绛夐牁鍩熴��
鍨嬭櫉锛歑C7VX415T-2FFG1157E
銆�銆�灏佽褰㈠紡锛欶FG1157
銆�銆�宸ヨ棟绡�(ji茅)榛烇細28nm
銆�銆�鍏ф牳闆诲锛�0.9V
銆�銆�I/O 闆诲锛�1.8V/2.5V/3.3V
銆�銆�閰嶇疆闁冨瓨闆诲锛�1.8V
銆�銆�FPGA 閭忚集鍠厓鏁�(sh霉)閲忥細绱� 415K
銆�銆�RAM 瀹归噺锛�2,164 Kb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2,736
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�氶亾鏁�(sh霉)锛�48
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛�600Mbps 鑷� 13.1Gbps
銆�銆�鏅傞悩绠＄悊妯″锛氶泦鎴� PLL 鍜� MMCM
銆�銆�婧害鑼冨湇锛氬晢妤�(y猫)绱氾紙0掳C 鑷� 85掳C锛夊拰宸ユキ(y猫)绱氾紙-40掳C 鑷� 100掳C锛�
銆�銆�鍔熻�楀吀鍨嬪�硷細瑕栬ō瑷堣�屽畾锛岄�氬父鍦ㄥ咕鐡﹁嚦骞惧崄鐡︿箣闁�
1. 楂樻�ц兘鏋舵锛歏irtex-7 FPGA 鍩轰簬楂樻�ц兘鐨� 28nm ASIC 宸ヨ棟鍒堕��锛屽叿鍌欐洿楂樼殑閭忚集瀵嗗害鍜屾洿浣庣殑鍔熻�椼��
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銆�銆�4. 澶ц(gu墨)妯￠倧杓硣婧愶細鎻愪緵瓒呴亷 415K 鐨勯倧杓柈鍏�锛屾豢瓒冲京闆滆ō瑷堥渶姹�銆�
銆�銆�5. 鍙摯灞曟�э細鏀寔澶氱ó澶栬ō鎺ュ彛锛屽寘鎷崈鍏嗕互澶恫(w菐ng) MAC銆佷笁妯″紡浠ュお缍�(w菐ng) MAC 鍜� Aurora 閺堣矾灞ょ瓑銆�
銆�銆�6. 鍏х疆瑾胯│宸ュ叿锛氭敮鎸� ChipScope Pro 绛夊祵鍏ュ紡閭忚集鍒嗘瀽鍎�鍔熻兘锛屾柟渚块枊鐧�(f膩)鍜岃瑭︺��
銆�銆�7. 闈堟椿鐨勯厤缃伕闋咃細鏀寔寰� SPI銆丅PI 鎴� PROM 瑷倷鍔犺級閰嶇疆鏁�(sh霉)鎿�(j霉)锛屽悓鏅傚吋瀹� JTAG 鎺ュ彛鐢ㄤ簬鍦ㄧ窔瑾胯│銆�
XC7VX415T-2FFG1157E 涓昏鎳夌敤浜庝互涓嬮牁鍩燂細
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銆�銆�5. 閱�(y墨)鐧傞浕瀛愶細瓒呰伈娉㈡垚鍍�銆丆T 鎺冩弿鏁�(sh霉)鎿�(j霉)閲嶅缓銆佸鏅傛偅鑰呯洠(ji膩n)鎺х郴绲�(t菕ng)銆�
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XC7VX415T-3FFG1157E
銆�銆�XC7VX415T-2FFG1761E
銆�銆�XC7VX415T-3FFG1761E
