鍣ㄤ欢椤炲瀷锛欶PGA
銆�銆�鍒剁▼宸ヨ棟锛�28nm
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 690,000
銆�銆�DSP Slice 鏁�(sh霉)閲忥細4,100
銆�銆�RAM 璩囨簮锛氱磩 32.6 Mb
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細72
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銆�銆�渚涢浕闆诲�擄細鏍稿績闆诲�� 1.0V锛岃紨鍔╅浕澹� 1.8V/2.5V/3.3V
銆�銆�灏佽�濆舰寮忥細FFG1761
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C
銆�銆�閫熷害绛夌礆锛�-1

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銆�銆�5. 鍙�鎿村睍鎬э細閫氶亷 PCI Express 绛夋帴鍙ｅ崝(xi茅)璀拌紩鏉捐垏鍏朵粬瑷�鍌欎簰鑱�(li谩n)銆�
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瑭� FPGA 鍣ㄤ欢鍙�寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂��
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XC7VX690T-2FFG1761I
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