鍨嬭櫉锛歑C7Z007S-2CLG400E
銆�銆�绯诲垪锛歓ynq-7000
銆�銆�CPU 鏍稿績锛氶洐鏍� ARM Cortex-A9
銆�銆�涓婚牷锛�667 MHz
銆�銆�FPGA 鏋舵��(g貌u)锛欰rtix-7
銆�銆�鍙�閰嶇疆閭忚集濉婏紙CLB锛夛細13320
銆�銆�DSP Slice 鏁�(sh霉)閲忥細110
銆�銆�Block RAM 鏁�(sh霉)閲忥細390 Kb
銆�銆�閰嶇疆 Flash锛氱劇鐗囧収(n猫i) Flash锛岄渶澶栫疆
銆�銆�I/O 鏁�(sh霉)閲忥細264
銆�銆�灏佽�濆舰寮忥細CLG400 (400-Pin Ceramic Land Grid Array)
銆�銆�婧�搴﹁寖鍦嶏��0掳C 鑷� 85掳C
銆�銆�宸ヤ綔闆诲�擄細鏍稿績闆诲�� 1.0V锛孖/O 闆诲�� 1.8V/2.5V/3.3V

XC7Z007S-2CLG400E 鎻愪緵浜嗛珮搴﹂泦鎴愬寲鐨勮В姹烘柟妗堬紝鍖呭惈浠ヤ笅涓昏�佺壒鎬э細
銆�銆�1. 闆嗘垚闆欐牳 ARM Cortex-A9 MPCore 铏曠悊鍣�锛屾敮鎸� NEON 鍜� FPU 鍔犻�燂紝鍏峰倷瀵�(sh铆)鏅�(sh铆)鎿嶄綔绯荤当(t菕ng)鏀�鎸佸拰楂橀�熻檿鐞嗚兘鍔涖��
銆�銆�2. 鍏�(n猫i)缃� FPGA 鏋舵��(g貌u)锛屽熀浜� Artix-7 绯诲垪锛屾彁渚涢潏娲荤殑纭�浠惰嚜瀹氱京鍔熻兘浠ュ��(sh铆)鐝�(xi脿n)绠楁硶鍔犻�熷拰鎺ュ彛鎿�(ku貌)灞�銆�
銆�銆�3. 鏀�鎸� AXI 绺界窔鍗�(xi茅)璀帮紝鏂逛究铏曠悊鍣ㄨ垏 FPGA 涔嬮枔鐨勯珮鏁堟暩(sh霉)鎿�(j霉)鍌宠几銆�
銆�銆�4. 鍏�(n猫i)閮ㄨ硣婧愯睈瀵�锛屽寘鎷� DSP Slice銆丅lock RAM 鍜屽垎甯冨紡 RAM锛屾豢瓒冲�氱ó鏁�(sh霉)瀛椾俊铏熻檿鐞嗛渶姹�銆�
銆�銆�5. 鏀�鎸佸�氱ó楂橀�熶覆琛屾帴鍙ｏ紝濡� Gigabit Ethernet銆丳CIe 鍜� SATA锛屽悓鏅�(sh铆)鍏煎�瑰偝绲�(t菕ng)骞惰�屾帴鍙ｃ��
銆�銆�6. 闆嗘垚闆绘簮绠＄悊妯″��锛岄檷浣庣郴绲�(t菕ng)寰�(f霉)闆滃害骞跺劒(y艒u)鍖栧姛鑰楄〃鐝�(xi脿n)銆�
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XC7Z007S-2CLG400E 鐨勬噳(y墨ng)鐢ㄥ牬鏅�娑佃搵澶氬��(g猫)闋�(l菒ng)鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷�鍕�(d貌ng)鍖栵細鐢ㄤ簬 PLC 鎺у埗鍣ㄣ�侀亱(y霉n)鍕�(d貌ng)鎺у埗鍣�銆佹��(j墨)鍣ㄨ�栬�虹瓑瑷�(sh猫)鍌�銆�
銆�銆�2. 閫氫俊瑷�(sh猫)鍌欙細閬╃敤浜庡皬鍨嬪熀绔�銆佽矾鐢卞櫒銆佷氦鎻涙��(j墨)绛夌恫(w菐ng)绲�(lu貌)鍩虹��(ch菙)瑷�(sh猫)鏂�銆�
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銆�銆�4. 閱�(y墨)鐧傚剙鍣�锛氬��(sh铆)鐝�(xi脿n)瓒呰伈娉㈣ō(sh猫)鍌欍�佺洠(ji膩n)璀�(h霉)鍎�绛夐珮鎬ц兘閱�(y墨)鐧傛噳(y墨ng)鐢�銆�
銆�銆�5. 姹借粖闆诲瓙锛氱敤浣� ADAS 杓斿姪椐曢�涚郴绲�(t菕ng)鎴栬粖杓変俊鎭�濞涙▊绯荤��(t菕ng)鐨勬牳蹇冭檿鐞嗗櫒銆�
銆�銆�6. 宓屽叆寮忚▓(j矛)绠楋細鍦ㄩ倞绶ｈ▓(j矛)绠楃瘈(ji茅)榛�(di菐n)涓�鍏呯��(d膩ng)涓绘帶鍠�鍏�锛屾彁渚涜▓(j矛)绠楄兘鍔涘拰 I/O 鎿�(ku貌)灞�銆�

XC7Z007S-1CLG400C, XC7Z007S-3CLG400I