鏅傞枔锛�2025/5/8 8:47:19
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XC7Z015-3CLG485I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Zynq-7000 绯诲垪鍙法绋� SoC 鑺墖涔嬩竴銆傝┎绯诲垪闆嗘垚浜嗛洐鏍� ARM Cortex-A9 铏曠悊鍣ㄥ拰 FPGA 鍙法绋嬮倧杓柈鍏�锛岃兘澶犳豢瓒冲祵鍏ュ紡绯荤当(t菕ng)涓皪楂樻�ц兘銆侀潏娲绘�т互鍙婁綆鍔熻�楃殑闇�姹�銆俋C7Z015 鐗瑰垾閬╃敤浜庨渶瑕佽純楂樿▓绠楄兘鍔涜垏纭欢鍔犻�熺殑鎳夌敤鍫存櫙锛屼緥濡傚伐妤�(y猫)鑷嫊鍖�銆侀�氫俊瑷倷銆侀啱(y墨)鐧傛垚鍍忓強姹借粖闆诲瓙绛夈��
鍨嬭櫉锛歑C7Z015-3CLG485I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歓ynq-7000
銆�銆�灏佽椤炲瀷锛欳LG485 (484 寮曡叧)
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�FPGA 閭忚集鍠厓鏁�(sh霉)閲忥細绱� 28K
銆�銆�RAM 璩囨簮锛氱磩 1.4Mb (BRAM)
銆�銆�DSP Slice 鏁�(sh霉)閲忥細180
銆�銆�铏曠悊鍣ㄦ灦妲嬶細闆欐牳 ARM Cortex-A9
銆�銆�涓婚牷鑼冨湇锛氶珮閬� 667 MHz
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O 闆诲锛�1.8V / 3.3V
銆�銆�閰嶇疆妯″紡锛歋lave Serial / Master SPI / JTAG
XC7Z015-3CLG485I 鐨勪富瑕佺壒榛炴槸鍏惰瀺鍚堜簡闆欐牳 ARM Cortex-A9 铏曠悊鍣ㄥ瓙绯荤当(t菕ng) (PS - Processing System) 鍜� Artix-7 绯诲垪 FPGA 鐨勫彲绶ㄧ▼閭忚集鍠厓 (PL - Programmable Logic)銆傞�欑ó鏋舵鍏佽ū鐢ㄦ埗鍦� PS 閮ㄥ垎閬嬭瀵︽檪鎿嶄綔绯荤当(t菕ng)鎴栧祵鍏ュ紡杌熶欢锛屽悓鏅傞�氶亷 PL 閮ㄥ垎瀵︾従(xi脿n)瀹氬埗鍖栫殑纭欢鍔犻�熷姛鑳�銆�
銆�銆�瑭茶姱鐗囨敮鎸佸绋瑷帴鍙ｏ紝鍖呮嫭 USB銆丳CIe銆丒thernet銆丼DIO銆丆AN 鍜� UART 绛�锛屾サ澶у湴鎿村睍浜嗗叾閬╃敤鑼冨湇銆傛澶�锛屽畠閭勫収(n猫i)缃簡 DDR3 鍏�(n猫i)瀛樻帶鍒跺櫒锛屼究浜庨�ｆ帴澶栭儴瀛樺劜鍣ㄤ互鎻愬崌绯荤当(t菕ng)鎬ц兘銆�
銆�銆�鍦ㄥ姛鑰楃鐞嗘柟闈紝XC7Z015 鎻愪緵鍕曟厠(t脿i)鍔熻�楄(di脿o)绡�(ji茅)鍔熻兘锛屽彲浠ラ嚌灏嶄笉鍚屽伐浣滆矤杓夊劒(y艒u)鍖栬兘婧愭秷鑰�銆傚苟涓旂敱浜庨噰鐢ㄤ簡 28nm 鍒剁▼宸ヨ棟锛岄�蹭竴姝ラ檷浣庝簡鏁撮珨鍔熻�楁按骞�銆�
銆�銆�闁嬬櫦(f膩)宸ュ叿鏂归潰锛岀敤鎴跺彲浠ラ�氶亷 Vivado 鎴� SDK 灏� XC7Z015 閫茶瑷▓鑸囪(di脿o)瑭︼紝寰炶�屽揩閫熷畬鎴愬緸姒傚康鍒扮敘(ch菐n)鍝佺殑杞�(zhu菐n)鍖�銆�
XC7Z015-3CLG485I 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖栵細鐢ㄤ簬閬嬪嫊鎺у埗銆佹鍣ㄤ汉瑕栬鍜屾暩(sh霉)鎿�(j霉)閲囬泦绛�銆�
銆�銆�2. 閫氫俊瑷倷锛氬鍩虹珯铏曠悊鍠厓銆佷俊铏熻(di脿o)鐞嗘ā濉�銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忥細瓒呰伈娉㈣ō鍌欍�丆T 鎺冩弿鍎�涓殑鍦栧儚铏曠悊鍠厓銆�
銆�銆�4. 姹借粖闆诲瓙锛氶珮绱氶椐涜紨鍔╃郴绲�(t菕ng) (ADAS) 涓殑鐩璀樺垾鑸囪矾寰戣(gu墨)鍔�銆�
銆�銆�5. 宓屽叆寮忚▓绠楋細渚挎敎寮忓剙鍣ㄥ剙琛�銆佺墿鑱�(li谩n)缍�(w菐ng)缍�(w菐ng)闂滅瓑銆�
銆�銆�6. 瑕栭牷铏曠悊锛氳闋荤法纰艰В纰�銆佸湒褰㈡覆鏌撳強澧炲挤鐝�(xi脿n)瀵︽妧琛撱��
XC7Z010-2CLG484I
銆�銆�XC7Z020-3CLG485I
銆�銆�XC7Z030-2FBG676I
