鑺�鐗囧瀷铏�(h脿o)锛歑C7Z020
銆�銆�灏佽�濆舰寮忥細CLG400
銆�銆�閫熷害绛夌礆(j铆)锛�-2
銆�銆�FPGA 閭忚集鍠�鍏冿細绱� 20,660 鍊�(g猫) CLB
銆�銆�閰嶇疆瀛樺劜(ch菙)鍣�锛�512KB Block RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細250 鍊�(g猫)
銆�銆�I/O 寮曡叧鏁�(sh霉)锛�384 鍊�(g猫)
銆�銆�鏀�鎸佺殑鏈�澶ч牷鐜囷細绱� 642 MHz
銆�銆�宸ヨ棟绡�(ji茅)榛�(di菐n)锛�28nm
銆�銆�宸ヤ綔闆诲�擄��0.9V 鏍稿績锛�1.0V I/O

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XC7Z010-2CLG400I
銆�銆�XC7Z030-2FBG676I
銆�銆�XC7Z100-2FFG900I