宸ヨ棟锛�28nm
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C鑷�+85掳C
銆�銆�鍏�(n猫i)鏍搁浕澹擄細1.0V
銆�銆�I/O闆诲�擄��1.8V/2.5V/3.3V
銆�銆�灏佽�濋�炲瀷锛欶BGA
銆�銆�寮曡叧鏁�(sh霉)锛�676
銆�銆�铏曠悊鍣�锛氶洐鏍窤RM Cortex-A9
銆�銆�涓婚牷锛�667MHz
銆�銆�绶╁瓨锛�2x 32KB L1 Data Cache, 2x 32KB L1 Instruction Cache, 512KB L2 Cache
銆�銆�FPGA閭忚集鍠�鍏冿細绱�45K鍊�
銆�銆�RAM璩囨簮锛氱磩2.2MB Block RAM
銆�銆�DSP Slice锛氱磩900鍊�
銆�銆�閰嶇疆妯″紡锛歋PI, BPI, PROM

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銆�銆�2. FPGA閮ㄥ垎鍏佽ū鐢ㄦ埗瀵�(sh铆)鐝�(xi脿n)瀹氬埗鍖栫殑纭�浠跺姞閫熷姛鑳斤紝渚嬪�傚湒鍍忚檿鐞嗙畻娉曟垨鏁�(sh霉)鎿�(j霉)鍔犲瘑銆�
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XC7Z045寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
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銆�銆�2. 宸ユキ(y猫)鑷�鍕曞寲锛氬彲鐢ㄤ簬閬�(y霉n)鍕曟帶鍒�銆佹��(j墨)鍣ㄤ汉鎶�琛�(sh霉)鍙婂伐妤�(y猫)鐗╄伅(li谩n)缍�(w菐ng)绛夐牁(l菒ng)鍩�銆�
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XC7Z030-1FBG676C
銆�銆�XC7Z020-1CLG484C
銆�銆�XC7Z010-1CLG400I