XC9572-10PQ100I 鏅�(sh铆)闁擄細2023/7/18 18:00:31 闁辫畝锛�529

鎻忚堪

XC9572-10PQ100I鏄竴娆鹃珮鎬ц兘CPLD锛屽彲鐐洪€氱敤閭忚集闆嗘垚鎻愪緵鍏堥€�(j矛n)鐨勭郴绲�(t菕ng)鍏�(n猫i)绶ㄧ▼鍜屾脯瑭﹀姛鑳姐€傚畠鐢卞洓鍊�(g猫)36V18鍔熻兘濉婄祫鎴�锛屾彁渚�1,600鍊�(g猫)鍙敤闁€锛屽偝鎾欢閬茬偤7.5ns銆傛敮鎸乷ne XC9500浠ヤ笂骞剁櫦(f膩)骞惰绶ㄧ▼锛屽苟鎻愪緵44閲漃LCC銆�84閲漃LCC銆�100閲漃QFP鍜�100閲漈QFP灏佽銆�

鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�	XC9572-10PQ100I
鎻忚堪	闆嗘垚闆昏矾CPLD 72MC 10NS 100QFP
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-CPLD(寰�(f霉)闆滅殑鍙法绋嬮倧杓ō(sh猫)鍌�)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	XC9500
鎵撳寘	鎵樼洡
闆绘簮-鍏�(n猫i)閮�	4.5V?5.5V
宸ヤ綔婧害	-40掳C?85掳C(TA)
鍖呰/绠�	100 BQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	100-PQFP(20x14)
鍩烘湰闆朵欢铏�	XC9572

鐢�(ch菐n)鍝佸湒鐗�

XC9572-10PQ100I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾槑	濉戞枡QFP-100
鍙法绋嬮倧杓鍨�	闁冨瓨PLD
鏈€澶ф檪(sh铆)閻橀牷鐜�	66.7鍏嗚但
绯荤当(t菕ng)鍏�(n猫i)鍙法绋�	鏄�
JESD-30浠ｇ⒓	R-PQFP-G100
JESD-609浠ｇ⒓	00
JTAG BST	鏄�
灏堢敤杓稿叆鏁�(sh霉)	0.0
I / O绶氭暩(sh霉)	72.0
瀹忓柈鍏冩暩(sh霉)	72.0
绔瓙鏁�(sh霉)	100
鏈€浣庡伐浣滄韩搴�	-40鈩�
鏈€楂樺伐浣滄韩搴�	85鈩�
绲勭箶	0鍊�(g猫)灏堢敤杓稿叆锛�72鍊�(g猫)I / O
杓稿嚭鍔熻兘	瀹忚渹绐�
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	QFP
鍖呰绛夋晥浠ｇ⒓	QFP100锛�.7X.9
鍖呰褰㈢媭	闀锋柟褰�
鍖呰褰㈠紡	FLATPACK
宄板€煎洖娴佹韩搴�(鈩�)	225
闆绘簮	3.3 / 5,5
鍌虫挱寤堕伈	10.0绱嶇
搴ч珮	3.4姣背
瀛愰鍒�	鍙法绋嬮倧杓櫒浠�
闆绘簮闆诲妯�(bi膩o)绋�	5.0浼�
鏈€灏忎緵闆婚浕澹�	4.5浼�
鏈€澶ч浕婧愰浕澹�	5.5浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
婧害绛夌礆	鐢�(ch菐n)妤�(y猫)
绲傜瀹屾垚	閷�/閴�(Sn85Pb15)
绲傜琛ㄦ牸	榉楃考鍨�
绔瓙闁撹窛	0.65姣背
绲傜浣嶇疆	QUAD
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	20.0姣背
瀵害	14.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙€鎱�(t脿i)	绗﹀悎RoHS瑕�(gu墨)瀹�
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

CAD妯″瀷

XC9572-10PQ100I绗﹁櫉

XC9572-10PQ100I鑵冲嵃

灏佽

XC9572-10PQ100I灏佽

鏇夸唬鍨嬭櫉

鍨嬭櫉	鍒堕€犲晢	鍝佸悕	鎻忚堪
XC9572-15PQ100C	Xilinx	CPLD鑺墖	1.6K Gates 72 Macro Cells 55.6MHz 0.5um Technology 5V 100Pin PQFP
XC9572-10PQ100C	Xilinx	CPLD鑺墖	1.6K Gates 72 Macro Cells 66.7MHz 0.5um Technology 5V 100Pin PQFP
XC9572-15PQ100I	Xilinx	CPLD鑺墖	1.6K Gates 72 Macro Cells 55.6MHz 0.5um Technology 5V 100Pin PQFP
XC9572-7PQG100C	Xilinx	CPLD鑺墖	1.6K Gates 72 Macro Cells 83.3MHz 0.5um Technology 5V 100Pin PQFP