绯诲垪锛欿intex UltraScale
銆�銆�FPGA 鍨嬭櫉(h脿o)锛歑CKU035
銆�銆�灏佽�濋��(l猫i)鍨嬶細FBGA 900
銆�銆�I/O 鏁�(sh霉)閲忥細684
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細35K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細1728
銆�銆�Block RAM 瀹归噺锛氱磩 11.1 Mb
銆�銆�灏�(zhu膩n)鐢ㄥ瓨鍎�(ch菙)鍣�锛�22.5 Mb eBRAM
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 16.3 Gbps
銆�銆�鍒剁▼宸ヨ棟锛�20nm
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +100掳C

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XCKU040-3FFVB1156E, XCKU060-2FFVB1156E