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鍣ㄤ欢椤炲瀷锛欶PGA
銆€銆€绯诲垪锛欿intex UltraScale
銆€銆€宸ヨ棟绡€(ji茅)榛�(di菐n)锛�20nm
銆€銆€閰嶇疆妯″紡锛歋ingle Boot, Master SPI
銆€銆€LUT鏁�(sh霉)閲忥細绱�384k
銆€銆€瀵勫瓨鍣ㄦ暩(sh霉)閲忥細绱�768k
銆€銆€DSP Slice鏁�(sh霉)閲忥細绱�2300
銆€銆€Block RAM瀹归噺锛氱磩54Mbit
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛氭渶楂橀仈(d谩)32.75Gbps
銆€銆€I/O Bank闆诲鑼冨湇锛�0.675V鑷�1.0V
銆€銆€灏佽褰㈠紡锛欶FGA1156

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