XCKU13P-3FFVE900E 鏅傞枔锛�2025/5/7 21:14:01 闁辫畝锛�26

XCKU13P-3FFVE900E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖涓殑涓€鍊嬪瀷铏�銆傝┎绯诲垪鑺墖涓昏闈㈠悜楂樺付瀵�銆佷綆鏅傚欢鐨勬噳(y墨ng)鐢ㄥ牬鏅紝閬╃敤浜庨€氫俊鍩虹(ch菙)瑷�(sh猫)鏂�銆佷俊铏熻檿鐞�銆佹暩(sh霉)鎿�(j霉)涓績鍔犻€熺瓑闋�(l菒ng)鍩熴€侹intex UltraScale 绯诲垪鍦ㄦ€ц兘鍜屾垚鏈箣闁撴彁渚涗簡鑹ソ鐨勫钩琛�锛孹CKU13P-3FFVE900E 闆嗘垚浜嗗ぇ閲忕殑 DSP 妯″銆丅RAM 浠ュ強楂樻€ц兘 I/O锛岃兘澶犳豢瓒冲绋京(f霉)闆滆▓(j矛)绠椾换鍕�(w霉)鐨勯渶姹�銆�
銆€銆€瑭插瀷铏熶腑鐨勫叿楂斿惈缇╁涓嬶細XCKU 琛ㄧず Kintex UltraScale 绯诲垪锛�13P 琛ㄧず瑭插櫒浠剁殑閭忚集鍠厓瑕�(gu墨)妯�锛�-3 琛ㄧず閫熷害绛夌礆锛孎(xi脿n)FVE900E 鍓囪〃绀哄皝瑁濋鍨嬪拰寮曡叧鏁�(sh霉)銆�

鍙冩暩(sh霉)

閭忚集鍠厓鏁�(sh霉)閲忥細220860
銆€銆€瀛樺劜鍣ㄨ硣婧愶細1140KB BRAM
銆€銆€DSP Slice 鏁�(sh霉)閲忥細2880
銆€銆€I/O 鏁�(sh霉)閲忥細744
銆€銆€閰嶇疆妯″紡锛歋electMAP 鍜� JTAG
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€灏佽椤炲瀷锛欶FVE900
銆€銆€閫熷害绛夌礆锛�-3

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XCKU13P-3FFVE900E 鎻愪緵浜嗗挤(qi谩ng)澶х殑骞惰铏曠悊鑳藉姏鍜岄潏娲荤殑鏋舵(g貌u)瑷�(sh猫)瑷�(j矛)锛屽叾闂�(gu膩n)閸电壒鎬у寘鎷細
銆€銆€1. 楂樻晥鐨� DSP 寮曟搸锛氭敮鎸侀珮閬�(d谩) 850 MHz 鐨勯亱(y霉n)琛岄牷鐜�锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑鏁�(sh霉)瀛�(xu茅)閬�(y霉n)绠楀拰淇¤櫉铏曠悊浠诲嫏(w霉)銆�
銆€銆€2. 澶у閲忕殑鍏�(n猫i)閮ㄥ瓨鍎插櫒锛氬寘鍚睈瀵岀殑 Block RAM 鍜屽垎甯冨紡 RAM 璩囨簮锛屽彲鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕鍜岀畻娉曞(sh铆)鐝�(xi脿n)銆�
銆€銆€3. 楂橀€熶覆琛屾敹鐧�(f膩)鍣細闆嗘垚澶氬€� GTY 鏀剁櫦(f膩)鍣ㄦā濉�锛屾敮鎸侀珮閬�(d谩) 32.75 Gbps 鐨勫偝杓搁€熺巼銆�
銆€銆€4. 鍙摯(ku貌)灞曟€э細鏀寔澶氳姱鐗囧爢鐤婏紙Stacked Silicon Interconnect锛夋妧琛�(sh霉)锛屽彲閫�(j矛n)涓€姝ュ鍔犻倧杓瘑搴﹀拰瀛樺劜瀹归噺銆�
銆€銆€5. 宓屽叆寮忚檿鐞嗗櫒鏀寔锛氬吋瀹� Xilinx 鐨� Zynq 骞宠嚭锛屽彲鑸� ARM Cortex 铏曠悊鍣ㄧ祼(ji茅)鍚堜娇鐢�锛屾彁渚涜粺纭欢鍗�(xi茅)鍚岃ō(sh猫)瑷�(j矛)鐨勮兘鍔�銆�
銆€銆€6. 浣庡姛鑰楄ō(sh猫)瑷�(j矛)锛氶€氶亷鍕曟厠(t脿i)闆绘簮绠＄悊鎶€琛�(sh霉)鍜屽劒(y艒u)鍖栫殑鏋舵(g貌u)瑷�(sh猫)瑷�(j矛)锛屾湁鏁堥檷浣庝簡鏁撮珨鍔熻€�銆�

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XCKU13P-3FFVE900E 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 閫氫俊瑷�(sh猫)鍌欙細濡傚熀绔欍€佽矾鐢卞櫒鍜屼氦鎻涙(j墨)绛�锛岀敤浜庡崝(xi茅)璀拌檿鐞嗐€佹暩(sh霉)鎿�(j霉)鍖呭垎椤炲拰娴侀噺绠＄悊銆�
銆€銆€2. 鏁�(sh霉)鎿�(j霉)涓績锛氫綔鐐哄姞閫熷崱鐨勬牳蹇冨櫒浠讹紝鐢ㄤ簬姗�(j墨)鍣ㄥ(xu茅)缈�(x铆)鎺ㄧ悊銆佸姞瀵嗚В瀵嗗拰鏁�(sh霉)鎿�(j霉)搴煡瑭㈠姞閫�銆�
銆€銆€3. 瑕栭牷铏曠悊锛氭敮鎸� 4K/8K 瑕栭牷绶ㄨВ纰煎拰鍦栧儚澧炲挤(qi谩ng)鍔熻兘锛岄仼鐢ㄤ簬寤ｆ挱绱氳闋昏ō(sh猫)鍌�銆�
銆€銆€4. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬瀵�(sh铆)鏅傚湒鍍忛噸寤哄拰鍒嗘瀽锛屾彁鍗囪ê鏂锋晥鐜�銆�
銆€銆€5. 宸ユキ(y猫)鑷嫊鍖栵細鐐洪亱(y霉n)鍕曟帶鍒跺拰姗�(j墨)鍣ㄤ汉绯荤当(t菕ng)鎻愪緵楂樻€ц兘瑷�(j矛)绠楀钩鑷�銆�
銆€銆€6. 娓│鑸囨脯閲忥細鐢ㄤ簬楂橀€熸暩(sh霉)鎿�(j霉)閲囬泦鍜屼俊铏熺敓鎴�銆�