鏅傞枔锛�2025/5/8 11:08:24
闁辫畝锛�27
XCKU15P-1FFVE1760E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� Kintex UltraScale 绯诲垪 FPGA 鑺墖涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鑺墖灏堢偤楂樻�ц兘瑷堢畻銆佺恫(w菐ng)绲�(lu貌)铏曠悊鍜屼俊铏熻檿鐞嗙瓑鎳夌敤鑰岃ō(sh猫)瑷�锛岄噰鐢� 20nm 鍒剁▼宸ヨ棟鍒堕��锛屽叿鍌欓珮閭忚集瀵嗗害銆佽睈瀵岀殑 DSP 妯″浠ュ強楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄨ硣婧�銆�
銆�銆�Kintex UltraScale 绯诲垪鍦ㄦ�ц兘鑸囨垚鏈箣闁撴彁渚涗簡鑹ソ鐨勫钩琛★紝閬╁悎澶氱ó涓珮绔噳鐢ㄩ渶姹�銆俋CKU15P-1FFVE1760E 鎻愪緵浜嗚純楂樼殑閭忚集璩囨簮鍜� I/O 璩囨簮锛屽悓鏅傛敮鎸佸妯ｇ殑閰嶇疆妯″紡鍜屾帴鍙ｆ婧栥��
鍨嬭櫉锛歑CKU15P-1FFVE1760E
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛欿intex UltraScale
銆�銆�鍒剁▼宸ヨ棟锛�20nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 139,200 鍊�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2,880 鍊�
銆�銆�Block RAM 瀹归噺锛�4,608 Kb
銆�銆�UltraRAM 瀹归噺锛�16 Mb
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細32 鍊�
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼鑼冨湇锛氭渶楂� 32.18 Gbps
銆�銆�I/O Bank 鏁�(sh霉)閲忥細40 鍊�
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.9V锛孖/O 闆诲渚濋厤缃�屽畾
銆�銆�灏佽椤炲瀷锛欶FVE1760
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCKU15P-1FFVE1760E 鐨勪富瑕佺壒鎬у寘鎷細
銆�銆�1. 楂樻�ц兘閭忚集绲�(ji茅)妲�(g貌u)锛氬熀浜� UltraScale 鏋舵(g貌u)锛屾彁渚涘寮风殑鏅傚簭鏀舵杺鑳藉姏锛屽苟鍎�(y艒u)鍖栦簡璺敱璩囨簮銆�
銆�銆�2. 寮峰ぇ鐨勬暩(sh霉)瀛椾俊铏熻檿鐞嗚兘鍔涳細闆嗘垚澶ч噺 DSP Slice锛屾敮鎸侀珮鏁堢殑娴粸閬嬬畻鍜屽畾榛為亱绠�锛岄仼鐢ㄤ簬寰╅洔绠楁硶瀵︾従(xi脿n)銆�
銆�銆�3. 楂橀�熶覆琛岄�ｆ帴锛氭敮鎸侀珮閬� 32.18 Gbps 鐨勬敹鐧�(f膩)鍣ㄩ�熺巼锛屾豢瓒虫柊涓�浠ｉ�氫俊鍗�(xi茅)璀扮殑闇�姹�銆�
銆�銆�4. 澶у閲忓瓨鍎茶硣婧愶細鍖呭惈 Block RAM 鍜� UltraRAM锛岄仼鍚堟暩(sh霉)鎿�(j霉)绶╁瓨鍜屽瓨鍎插瘑闆嗗瀷鎳夌敤銆�
銆�銆�5. 闈堟椿鐨� I/O 鏀寔锛氭彁渚涘绋� I/O 妯欐簴鍏煎鎬э紝鑳藉閬╂噳涓嶅悓鎳夌敤鍫存櫙銆�
銆�銆�6. 鍏�(n猫i)缃‖鏍告ā濉婏細鏀寔 PCIe Gen3 纭牳妯″锛岀啊鍖栫郴绲�(t菕ng)瑷�(sh猫)瑷堝苟鎻愰珮鎬ц兘銆�
銆�銆�7. 鍙潬鎬у拰浣庡姛鑰楋細閫氶亷楂樼礆闆绘簮绠＄悊鎶�琛�(sh霉)闄嶄綆鏁撮珨鍔熻�楋紝鍚屾檪纰轰繚鍣ㄤ欢鍦ㄦ儭鍔ｇ挵(hu谩n)澧冧笅鐨勫彲闈犳��銆�
XCKU15P-1FFVE1760E 寤ｆ硾鎳夌敤浜庝互涓嬮牁(l菒ng)鍩燂細
銆�銆�1. 閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂斤細濡傜劇绶氬熀绔欍�佹湁绶氭帴鍏ヨō(sh猫)鍌欏拰鏍稿績缍�(w菐ng)瑷�(sh猫)鍌�銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬缍�(w菐ng)绲�(lu貌)鍖呰檿鐞嗐�佸姞瀵嗚В瀵嗗強娣卞害瀛哥繏鎺ㄧ悊浠诲嫏銆�
銆�銆�3. 瑕栭牷铏曠悊锛氭敮鎸侀珮鍒嗚鲸鐜囪闋荤法纰�銆佽В纰煎拰鍦栧儚鍒嗘瀽銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細瀵︽檪鎺у埗銆侀亱鍕曟帶鍒跺拰宸ユキ(y猫)鐗╄伅(li谩n)缍�(w菐ng)銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細蹇�熸暩(sh霉)鎿�(j霉)閲囬泦鑸囧湒鍍忛噸寤�銆�
銆�銆�6. 娓│娓噺锛氶珮閫熸暩(sh霉)鎿�(j霉)閲囬泦鍜屼俊铏熺敓鎴�銆�
銆�銆�7. 宓屽叆寮忚瑕猴細瑷堢畻姗熻瑕虹畻娉曠‖浠跺姞閫�銆�
XCKU15P-2FFVE1760E
銆�銆�XCKU15P-3FFVE1760E
