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灏佽锛欶FVA676
銆€銆€閰嶇疆妯″紡锛歋lave Serial, Master Parallel
銆€銆€I/O Bank闆诲锛�1.8V
銆€銆€鍏�(n猫i)鏍搁浕澹擄細0.95V~1.0V
銆€銆€FPGA绯诲垪锛欿intex UltraScale
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€閭忚集鍠厓鏁�(sh霉)閲忥細绱�93K
銆€銆€DSP Slice鏁�(sh霉)閲忥細1560
銆€銆€Block RAM瀹归噺锛氱磩5.6Mb
銆€銆€鐢ㄦ埗闁冨瓨澶у皬锛歂/A
銆€銆€鏀剁櫦(f膩)鍣ㄩ€熺巼锛氭渶楂橀仈(d谩)32.75Gbps

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