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XCKU3P-2FFVA676E 鏄竴娆惧熀浜� Xilinx UltraScale 鏋舵鐨� FPGA 鑺墖锛屽爆浜� Kintex UltraScale 绯诲垪銆傝┎绯诲垪鍣ㄤ欢閲濆皪楂樻�ц兘鍜屼綆鍔熻�楅�茶浜嗗劒(y艒u)鍖�锛岄仼鐢ㄤ簬閫氫俊銆佽埅绌鸿埅澶�銆佸唬鎾互鍙婃脯瑭︽脯閲忕瓑澶氱ó闋樺煙銆傛鍨嬭櫉鍏锋湁璞愬瘜鐨勯倧杓硣婧�銆佹暩(sh霉)瀛椾俊铏熻檿鐞� (DSP) 妯″銆佸瓨鍎插櫒鍜岄珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屼娇鍏惰兘澶犳豢瓒冲京闆滅郴绲�(t菕ng)瑷▓鐨勯渶姹傘��
銆�銆�瑭茶姱鐗囬噰鐢ㄥ厛閫茬殑 FinFET 鍒剁▼鎶�琛撳埗閫�锛屾敮鎸佸绋厤缃ā寮忓拰闈堟椿鐨� I/O 妯欐簴锛岄仼鍚堥渶瑕侀珮鍚炲悙閲忓拰浣庡欢閬茬殑鎳夌敤鍫存櫙銆�
鍨嬭櫉锛歑CKU3P-2FFVA676E
銆�銆�鏋舵锛歎ltraScale
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 145K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細2880
銆�銆�Block RAM 瀹归噺锛殈11.6Mb
銆�銆�UltraRAM 瀹归噺锛殈6Mb
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂橀仈 32.75Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶氭敮鎸� 744 鍊嬬敤鎴� I/O
銆�銆�灏佽椤炲瀷锛欶FVA676
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�鍒剁▼宸ヨ棟锛�20nm
XCKU3P-2FFVA676E 鎻愪緵浜嗗挤澶х殑鎬ц兘鍜岄潏娲绘��锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧愶細瑭插瀷铏熷寘鍚ぇ绱� 145K 鐨勯倧杓柈鍏�锛屽彲浠ュ鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�2. 寮峰ぇ鐨� DSP 鍔熻兘锛�2880 鍊� DSP Slice 鏀寔楂樻晥娴粸閬嬬畻鍜屾烤娉㈠櫒瑷▓锛岀壒鍒ラ仼鍚堣▓绠楀瘑闆嗗瀷鎳夌敤銆�
銆�銆�3. 澶у閲忓瓨鍎插櫒锛氱祼鍚� Block RAM 鍜� UltraRAM 鎶�琛�锛屾彁渚涢珮閬� ~17.6Mb 鐨勭墖涓婂瓨鍎茶兘鍔涳紝鐢ㄤ簬鏁�(sh霉)鎿�(j霉)绶╂矕鍜屾煡鎵捐〃銆�
銆�銆�4. 楂橀�熶覆琛岄�ｆ帴锛氶泦鎴愬璺敹鐧�(f膩)鍣紝鏀寔楂橀仈 32.75Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛屾豢瓒虫柊涓�浠ｉ�氫俊鍗�(xi茅)璀伴渶姹傘��
銆�銆�5. 闈堟椿鐨� I/O 鏀寔锛氬吋瀹瑰绋婧栵紙濡� LVCMOS銆丩VDS 绛夛級锛屽苟鍏峰倷鍕曟厠(t脿i) I/O 閰嶇疆鍔熻兘銆�
銆�銆�6. 鍏х疆鏅傞悩绠＄悊鍠厓锛氭彁渚� PLL 鍜� MMCM 妯″浠ョ敓鎴愮簿纰虹殑鏅傞悩淇¤櫉銆�
銆�銆�7. 鍏堥�茬殑闆绘簮绠＄悊绯荤当(t菕ng)锛氶�氶亷鍒嗗崁(q奴)渚涢浕鍜屽嫊鎱�(t脿i)鍔熻�楀劒(y艒u)鍖栭檷浣庢暣楂旇兘鑰�銆�
銆�銆�8. 鍙潬鎬у寮凤細鏀寔鍠簨浠剁炕杞� (SEU) 妾㈡脯鑸囩尘姝ｆ鍒讹紝鎻愰珮鍦ㄦ儭鍔ｇ挵(hu谩n)澧冧笅鐨勯亱琛岀┅(w臎n)瀹氭��銆�
XCKU3P-2FFVA676E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬鐒＄窔鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙涓殑淇¤櫉铏曠悊鍜屽崝(xi茅)璀拌綁鎻�銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鍙敤浜庢暩(sh霉)鎿�(j霉)搴煡瑭㈠姞閫�銆佺恫绲″畨鍏ㄨ檿鐞嗙瓑浠诲嫏銆�
銆�銆�3. 閱�(y墨)鐧傛垚鍍忚ō鍌欙細鏀寔瀵︽檪鍦栧儚铏曠悊鍜屾暩(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細瀵︾従(xi脿n)寰╅洔鐨勬帶鍒剁畻娉曞拰閬嬪嫊鎺у埗銆�
銆�銆�5. 鑸┖鑸ぉ锛氭豢瓒冲皪楂樺彲闈犳�у拰鎶楄蓟灏勬�ц兘鐨勯渶姹�銆�
銆�銆�6. 娓│鑸囨脯閲忓剙鍣細鐢ㄤ簬楂樻�ц兘绀烘尝鍣ㄣ�佷俊铏熺櫦(f膩)鐢熷櫒绛夊姛鑳芥ā濉�銆�
XCKU5P-2FFVA676E
銆�銆�XCKU7P-2FFVA676E
