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XCKU5P-3FFVA676E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale 绯诲垪 FPGA 鑺墖锛岄噰鐢� 20nm 宸ヨ棟鍒堕��銆傝┎鑺墖鍏锋湁楂樻�ц兘銆侀珮瀵嗗害鍜屼綆鍔熻�楃殑鐗归粸锛岄仼鐢ㄤ簬閫氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻��銆佽闋昏檿鐞�銆佸伐妤�(y猫)鑷嫊鍖栧拰鑸┖鑸ぉ绛夐牁鍩�銆�
銆�銆�鍏跺収(n猫i)閮ㄦ灦妲嬪寘鎷倧杓柈鍏�銆丏SP 妯″銆佸瓨鍎插櫒璩囨簮浠ュ強楂橀�熸敹鐧�(f膩)鍣ㄧ瓑澶氱ó纭牳 IP锛岃兘澶犳敮鎸佸京闆滅殑瑷▓闇�姹�銆�
鍨嬭櫉锛歑CKU5P-3FFVA676E
銆�銆�宸ヨ棟锛�20nm
銆�銆�灏佽锛欶FVA676
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 54K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 2880
銆�銆�Block RAM 瀹归噺锛氱磩 2790KB
銆�銆�閰嶇疆闁冨瓨锛氫笉鍏�(n猫i)缃�
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O 寮曡叧鏁�(sh霉)锛氭渶澶� 504
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
XCKU5P-3FFVA676E 灞簬 Kintex UltraScale 绯诲垪锛屼富瑕佺壒榛炲涓嬶細
銆�銆�1. 楂樻�ц兘閭忚集绲愭锛屾敮鎸侀珮閬� 1GHz 鐨勬檪閻橀牷鐜�銆�
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銆�銆�3. 鏀寔澶氱ó鎺ュ彛鍗�(xi茅)璀�锛屽 PCIe Gen3銆丆PRI銆丣ESD204B 绛夈��
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XCKU5P-3FFVA676E 寤ｆ硾鎳夌敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛屼緥濡� 5G 鍩虹珯涓殑鍩哄付铏曠悊鍠厓銆�
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銆�銆�3. 瑕栭牷寤ｆ挱瑷倷锛屾敮鎸佸鏅傚湒鍍忕法纰艰垏瑙ｇ⒓銆�
銆�銆�4. 閱�(y墨)鐧傚奖鍍忚ō鍌�锛屾彁渚涢珮鏁堢殑鍦栧儚閲嶅缓绠楁硶銆�
銆�銆�5. 宸ユキ(y猫)鎺у埗鑸囪嚜鍕曞寲锛屽鐝�(xi脿n)寰╅洔鐨勯亱鍕曟帶鍒剁畻娉曘��
銆�銆�6. 鑸┖鑸ぉ鍙婂湅闃查牁鍩�锛屾豢瓒抽珮鍙潬鎬ц姹傜殑浠诲嫏銆�
XCKU5P-2FFVA676E
銆�銆�XCKU5P-1FFVA676E
