XCV100-5BG256I 鏅�(sh铆)闁擄細2023/7/18 18:04:55 闁辫畝锛�956

鎻忚堪

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鐢�(ch菐n)鍝佹杩�

鐢�(ch菐n)鍝佸瀷铏�(h脿o)	XCV100-5BG256I
鎻忚堪	闆嗘垚闆昏矾FPGA 180 I / O 256BGA
鍒嗛	闆嗘垚闆昏矾(IC)锛屽祵鍏ュ紡-FPGA(鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪)
鍒堕€犲晢	Xilinx鍏徃
绯诲垪	Virtex?
鎵撳寘	鎵樼洡
闆诲-闆绘簮	2.375V?2.625V
宸ヤ綔婧害	-40掳C?100掳C(TJ)
鍖呰/绠�	256-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏寘瑁�	256-PBGA(27x27)
鍩烘湰闆朵欢铏�(h脿o)	XCV100

鐢�(ch菐n)鍝佸湒鐗�

XCV100-5BG256I

瑕�(gu墨)鏍煎弮鏁�(sh霉)

鍒堕€犲晢鍖呰瑾槑	BGA-256
鍙法绋嬮倧杓鍨�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
鏈€澶ф檪(sh铆)閻橀牷鐜�	294.0鍏嗚但
CLB-Max鐨勭祫鍚堝欢閬�	0.7绱嶇
JESD-30浠ｇ⒓	S-PBGA-B256
JESD-609浠ｇ⒓	00
绺絉AM浣�	40960
CLB鏁�(sh霉)閲�	600.0
绛夋晥闁€鏁�(sh霉)	108904.0
杓稿叆鏁�(sh霉)閲�	180.0
閭忚集鍠厓鏁�(sh霉)	2700.0
杓稿嚭鏁�(sh霉)閲�	180.0
绔瓙鏁�(sh霉)	256
绲勭箶	600 CLBS锛�108904闁€
鍖呰涓婚珨鏉愭枡	濉戞枡/鐠�(hu谩n)姘фü鑴�
鍖呰浠ｇ⒓	BGA
鍖呰绛夋晥浠ｇ⒓	BGA256,20X20,50
鍖呰褰㈢媭	鍥涙柟褰�
鍖呰褰㈠紡	缍�(w菐ng)鏍奸櫍鍒�
宄板€煎洖娴佹韩搴�(鈩�)	225
闆绘簮	1.5 / 3.3,2.5
搴ч珮	2.55姣背
瀛愰鍒�	鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪
闆绘簮闆诲妯�(bi膩o)绋�	2.5浼�
鏈€灏忎緵闆婚浕澹�	2.375浼�
鏈€澶ч浕婧愰浕澹�	2.625浼�
瀹夎椤炲瀷	琛ㄩ潰璨艰
鎶€琛�(sh霉)	CMOS
绲傜瀹屾垚	閷�/閴�(Sn63Pb37)
绲傜琛ㄦ牸	鐞�
绔瓙闁撹窛	1.27姣背
绲傜浣嶇疆	搴曢儴
鏅�(sh铆)闁揁宄板€煎洖娴佹韩搴�-鏈€澶у€�(绉�)	30
闀峰害	27.0姣背
瀵害	27.0姣背

鐠�(hu谩n)澧冭垏鍑哄彛鍒嗛

RoHS鐙€鎱�(t脿i)绗﹀悎	RoHS瑕�(gu墨)瀹�
姘村垎鏁忔劅鎬ф按骞�(MSL)	3(168灏忔檪(sh铆))

CAD妯″瀷

XCV100-5BG256I绗﹁櫉(h脿o)

XCV100-5BG256I鑵冲嵃

灏佽

XCV100-5BG256I灏佽

鏇夸唬鍨嬭櫉(h脿o)

鍨嬭櫉(h脿o)	鍒堕€犲晢	鍝佸悕	鎻忚堪
XCV100-4BG256I	璩介潏鎬�	FPGA鑺墖	256-BBGA 108904Gate 2.5V 180IO
XCV100-5BG256C	璩介潏鎬�	FPGA鑺墖	256-BBGA 108904Gate 2.5V 180IO
XCV100-6BG256C	璩介潏鎬�	FPGA鑺墖	108.904K Gates 2700 Cells 333MHz 0.22um Technology 2.5V 256Pin
XCV100-4BG256C	璩介潏鎬�	FPGA鑺墖	2.5V 108904gate 180io