XCVU11P-L2FLGF1924E 鏅�(sh铆)闁擄細2025/5/29 10:10:58 闁辫畝锛�10

XCVU11P-L2FLGF1924E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜� 16nm FinFET 鍒剁▼鎶€琛�(sh霉)銆傝┎鑺墖鍏锋湁楂樺瘑搴﹂倧杓柈鍏冦€侀珮閫熶覆琛屾敹鐧�(f膩)鍣ㄥ拰璞愬瘜鐨� DSP Slice锛岄仼鐢ㄤ簬楂樻€ц兘瑷�(j矛)绠�銆佹暩(sh霉)鎿�(j霉)涓績鍔犻€�銆佺恫(w菐ng)绲�(lu貌)閫氫俊浠ュ強宓屽叆寮忚瑕虹瓑闋�(l菒ng)鍩�銆�
銆€銆€瑭插瀷铏熷爆浜� Virtex UltraScale+ 绯诲垪锛屼富瑕侀嚌灏嶉渶瑕佸ぇ閲忔暩(sh霉)鎿�(j霉)铏曠悊鐨勬噳(y墨ng)鐢ㄥ牬鏅�锛屾彁渚涙サ楂樼殑闆嗘垚搴﹁垏鎬ц兘琛ㄧ従(xi脿n)銆�

鍙冩暩(sh霉)

绯诲垪锛歏irtex UltraScale+
銆€銆€鍒剁▼宸ヨ棟锛�16nm
銆€銆€灏佽椤炲瀷锛欶G1924E
銆€銆€閰嶇疆瀛樺劜鍣細Flash
銆€銆€CLB 鏁�(sh霉)閲忥細359840
銆€銆€DSP Slice 鏁�(sh霉)閲忥細7200
銆€銆€Block RAM 鏁�(sh霉)閲忥細2760
銆€銆€UltraRAM 鏁�(sh霉)閲忥細1620
銆€銆€PCIE 妯″鏁�(sh霉)閲忥細8
銆€銆€GTY 鏀剁櫦(f膩)鍣ㄩ€氶亾鏁�(sh霉)锛�104
銆€銆€宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆€銆€渚涢浕闆诲锛�1.0V 鏍稿績锛�1.8V I/O

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