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XCVU125-2FLVA2104E 鏄敱 Xilinx 鍏徃鐢熺敘(ch菐n)鐨勪竴娆� UltraScale+ 绯诲垪 FPGA 鑺墖锛岄噰鐢� 16nm FinFET 鍒剁▼宸ヨ棟銆傝┎鍣ㄤ欢鍏峰倷楂橀倧杓瘑搴�銆佽睈瀵岀殑 DSP Slice 鍜� Block RAM 璩囨簮锛屼互鍙婇潏娲荤殑 I/O 鎺ュ彛閰嶇疆鑳藉姏銆傚畠寤ｆ硾鎳夌敤浜庨珮鎬ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻��銆佸湒鍍忚檿鐞嗗拰宸ユキ(y猫)鑷嫊鍖栫瓑闋樺煙銆�
銆�銆�UltraScale+ 绯诲垪閫氶亷闆嗘垚 HBM锛圚igh Bandwidth Memory锛夊拰 ACAP锛圓daptive Compute Acceleration Platform锛夋妧琛�锛岀偤鐢ㄦ埗鎻愪緵浜嗗崜瓒婄殑鎬ц兘鑸囧姛鑰楀劒(y艒u)鍖栥��
鍨嬭櫉锛歑CVU125-2FLVA2104E
銆�銆�绯诲垪锛歎ltraScale+
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 125 钀��
銆�銆�DSP Slice 鏁�(sh霉)閲忥細7800 鍊�
銆�銆�Block RAM 瀹归噺锛氱磩 32.9 Mb
銆�銆�DDR 鏀寔锛欴DR4, LPDDR4
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶ф敮鎸� 1840 鍊嬬敤鎴� I/O
銆�銆�灏佽椤炲瀷锛欶LGA (Fine Line Grid Array)
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCVU125-2FLVA2104E 鎿佹湁寮峰ぇ鐨勫苟琛岃檿鐞嗚兘鍔涘拰鍙法绋嬫��锛岄仼鍚堝京闆滅畻娉曠殑纭欢瀵︾従(xi脿n)銆傚叾涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺害闈堟椿鐨勬灦妲嬭ō瑷�锛屽厑瑷辩敤鎴舵牴鎿�(j霉)闇�姹傚嫊鎱�(t脿i)瑾�(di脿o)鏁磋硣婧愰厤缃�銆�
銆�銆�2. 鍏�(n猫i)缃� PCIe Gen4 纭牳妯″锛屾敮鎸侀珮閬� x16 鐨勯張璺付瀵��
銆�銆�3. 鎻愪緵灏嶅绋帴鍙ｅ崝(xi茅)璀扮殑鏀寔锛屼緥濡備互澶恫(w菐ng) MAC銆両nterlaken 鍜� Aurora銆�
銆�銆�4. 寮峰ぇ鐨勬檪閻樼鐞嗗伐鍏�锛岀⒑淇濈郴绲�(t菕ng)绌�(w臎n)瀹氶亱琛�銆�
銆�銆�5. 鍏�(n猫i)閮ㄩ泦鎴愪簡瀹夊叏鍟熷嫊鍔熻兘锛屼繚璀� IP 涓嶈闈炴硶寰╁埗鎴栫鏀�銆�
銆�銆�6. 鏀寔澶氳姱鐗囧爢鐤婃妧琛�锛岄�蹭竴姝ユ摯灞曚簡瀛樺劜甯跺鍜屽閲�銆�
銆�銆�XCVU125-2FLVA2104E 鐨勯珮鎬ц兘浣垮叾鎴愮偤鐪惧楂樼鎳夌敤鐨勭悊鎯抽伕鎿�銆�
閫欐 FPGA 琚唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鐢ㄤ簬鏁�(sh霉)鎿�(j霉)搴煡瑭�銆佹悳绱㈢储寮曠瓑浠诲嫏鐨勭‖浠跺姞閫�銆�
銆�銆�2. 缍�(w菐ng)绲￠�氫俊锛氶仼鐢ㄤ簬璺敱鍣�銆佷氦鎻涙涓殑娴侀噺绠＄悊鍜屾暩(sh霉)鎿�(j霉)鍖呭垎椤炵瓑鍔熻兘銆�
銆�銆�3. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細鏀寔瀵︽檪瑕栭牷娴佸垎鏋愩�佸寮风従(xi脿n)瀵﹀拰瑷堢畻姗熻瑕�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鐐烘鍣ㄤ汉鎺у埗銆侀亱鍕曡(gu墨)鍔冩彁渚涢珮閫熶俊铏熻檿鐞嗚兘鍔�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細鐢ㄤ簬瓒呰伈娉�銆丆T 鎺冩弿瑷倷鐨勬暩(sh霉)鎿�(j霉)閲囬泦鑸囬噸寤恒��
銆�銆�6. 楂樻�ц兘瑷堢畻锛氳В姹虹瀛镐豢鐪�銆侀噾铻嶅缓妯＄瓑闋樺煙鐨勫瘑闆嗗瀷瑷堢畻鍟忛銆�
XCVU13P-2FLGA2104E
銆�銆�XCVU11P-2FLGA2104E
