鍨嬭櫉锛歑CVU125-2FLVB2104I
銆�銆�鍝佺墝锛歑ilinx
銆�銆�绯诲垪锛歏irtex UltraScale
銆�銆�鍒剁▼宸ヨ棟锛�20nm
銆�銆�閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 125K
銆�銆�RAM 瀹归噺锛�28.6Mb
銆�銆�DSP Slice 鏁�(sh霉)閲忥細3600
銆�銆�IO 鏁�(sh霉)閲忥細鏈�澶ф敮鎸� 1144 鍊嬬敤鎴� IO
銆�銆�鏅傞悩绠＄悊璩囨簮锛歁MCM 鍜� PLL
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂樻敮鎸� 28Gbps
銆�銆�灏佽�濆舰寮忥細FLGA锛團ine Line Grid Array锛�
銆�銆�鏍稿績闆诲�擄��0.9V
銆�銆�I/O 闆诲�擄��1.0V 鎴� 1.2V
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏細宸ユ��(y猫)绱氾紙-40掳C 鑷� +100掳C锛�

XCVU125-2FL鐗规�у寘鎷�锛�
銆�銆�1. 楂樻�ц兘鐨勯倧杓�璩囨��锛屾敮鎸佸京(f霉)闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕�(w霉)銆�
銆�銆�2. 鍏�(n猫i)缃�澶氶��(d谩) 3600 鍊� DSP Slice锛岄仼鍚堟诞榛�(di菐n)閬�(y霉n)绠楀拰鐭╅櫍瑷�(j矛)绠楃瓑楂樺瘑搴︽暩(sh霉)瀛�(xu茅)鎿嶄綔銆�
銆�銆�3. 鎻愪緵澶氱ó椤炲瀷鐨勫瓨鍎插櫒璩囨簮锛屽�� Block RAM 鍜� Distributed RAM锛屾豢瓒充笉鍚岀殑鏁�(sh霉)鎿�(j霉)绶╁瓨闇�姹�銆�
銆�銆�4. 闆嗘垚浜嗗�氬�嬮珮閫熶覆琛屾敹鐧�(f膩)鍣ㄩ�氶亾锛屾敮鎸佸緸 1Gbps 鍒� 28Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼銆�
銆�銆�5. 鏀�鎸� PCIe Gen3 鍗�(xi茅)璀帮紝鎻愪緵楂樻晥鐨勪富姗�(j墨)鎺ュ彛閫ｆ帴鑳藉姏銆�
銆�銆�6. 鎻愪緵闈堟椿鐨勬檪閻樼�＄悊鍜屼綆鎶栧嫊鎬ц兘锛岀⒑淇濈郴绲�(t菕ng)鐨勭┅(w臎n)瀹氭�с��
銆�銆�7. 鍕曟厠(t脿i)鍔熻兘浜ゆ彌鎶�琛�(sh霉)鍏佽ū灏� FPGA 鐨勯儴鍒嗗崁(q奴)鍩熼��(j矛n)琛岄噸鏂伴厤缃�锛屽緸鑰屾笡灏戠‖浠惰硣婧愬崰鐢ㄥ苟鎻愰珮鑳芥晥銆�

瑭茶姱鐗囧唬娉涙噳(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆�銆�1. 楂樻�ц兘瑷�(j矛)绠� (HPC)锛岀敤浜庣�戝��(xu茅)浠跨湡銆佹暩(sh霉)鎿�(j霉)鍒嗘瀽鍜屼汉宸ユ櫤鑳芥帹鐞�銆�
銆�銆�2. 缍�(w菐ng)绲�(lu貌)閫氫俊鍩虹��(ch菙)瑷�(sh猫)鏂�锛屼緥濡傝矾鐢卞櫒銆佷氦鎻涙��(j墨)鍜屽熀绔欒ō(sh猫)鍌欍��
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓�蹇冨姞閫熷崱锛屾彁渚涘畾鍒跺寲鐨勮▓(j矛)绠楀姞閫熻В姹烘柟妗�銆�
銆�銆�4. 宸ユキ(y猫)鑷�鍕曞寲鑸囨帶鍒�锛屽��(sh铆)鐝�(xi脿n)瀵�(sh铆)鏅傛暩(sh霉)鎿�(j霉)閲囬泦鍜岃檿鐞�銆�
銆�銆�5. 閱�(y墨)鐧傚奖鍍忚ō(sh猫)鍌欙紝濡� CT 鎺冩弿鍎�鍜岃秴鑱叉尝鎴愬儚绯荤当(t菕ng)涓�鐨勫湒鍍忚檿鐞�銆�
銆�銆�6. 闆烽仈(d谩)鍜岃��(w猫i)鏄熼�氫俊绯荤当(t菕ng)锛屾彁渚涗俊铏熻檿鐞嗗拰鍗�(xi茅)璀拌綁(zhu菐n)鎻涘姛鑳�銆�

XCVU13P-2FLGA2104E, XC7VX690T-2FFG1761C