XCVU13P-2FIGD2104I 鏅�(sh铆)闁擄細2025/5/20 15:22:31 闁辫畝锛�20

XCVU13P-2FIGD2104I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜� 16nm FinFET 宸ヨ棟鍒堕€�銆傝┎鍣ㄤ欢鍏锋湁楂橀倧杓瘑搴︺€佸ぇ瀹归噺鐨勫祵鍏ュ紡瀛樺劜(ch菙)鍣ㄥ拰 DSP 妯″锛屽悓鏅�(sh铆)鏀寔澶氱ó楂橀€熶覆琛屾帴鍙�銆傚叾涓昏鎳�(y墨ng)鐢ㄩ牁(l菒ng)鍩熷寘鎷恫(w菐ng)绲�(lu貌)閫氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻€�銆佸湒鍍忚檿鐞嗕互鍙婇珮鎬ц兘瑷�(j矛)绠楃瓑銆�
銆€銆€姝ゅ瀷铏�(h脿o)涓殑鍏烽珨鍚京濡備笅锛歑CVU 琛ㄧず灞簬 Virtex UltraScale+ 绯诲垪锛�13P 琛ㄧず FPGA 鐨勮(gu墨)妯＄瓑绱�(j铆)锛�2 琛ㄧず閫熷害绛夌礆(j铆)锛孎(xi脿n)IGD2104 琛ㄧず灏佽椤炲瀷鐐� 2104 寮曡叧鐨� FCBGA 灏佽锛孖琛ㄧず鍟嗙敤婧害鑼冨湇锛�0掳C 鑷� 85掳C锛�銆�

鍙冩暩(sh霉)

閭忚集鍠厓鏁�(sh霉)閲忥細绱� 2 鐧捐惉鍊�(g猫)
銆€銆€瀛樺劜(ch菙)鍣ㄨ硣婧愶細230MB 宓屽叆寮忓瓨鍎�(ch菙)鍣�
銆€銆€DSP Slice 鏁�(sh霉)閲忥細7200 鍊�(g猫)
銆€銆€I/O 寮曡叧鏁�(sh霉)锛�1728 鍊�(g猫)
銆€銆€閰嶇疆妯″紡锛歋electMAP 鍜� Master/Slave SPI
銆€銆€宸ヤ綔闆诲锛氭牳蹇冮浕澹� 0.85V锛岃紨鍔╅浕澹� 1.0V
銆€銆€鏈€澶у姛鑰楋細绱� 40W
銆€銆€灏佽椤炲瀷锛欶CBGA
銆€銆€寮曡叧鏁�(sh霉)锛�2104
銆€銆€宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C

鐗规€�

XCVU13P-2FIGD2104I 鎻愪緵浜嗗挤(qi谩ng)澶х殑鍙法绋嬮倧杓硣婧愬拰闈堟椿鐨勭‖浠舵灦妲�(g貌u)锛岄仼鐢ㄤ簬寰�(f霉)闆滅郴绲�(t菕ng)瑷�(sh猫)瑷�(j矛)銆傚叾鐗规€у寘鎷細
銆€銆€1. 楂樻€ц兘锛氶噰鐢� 16nm 鍒剁▼宸ヨ棟锛屽叿鍌欐洿楂樼殑閬�(y霉n)琛岄牷鐜囧拰鏇翠綆鐨勫姛鑰�銆�
銆€銆€2. 澶у閲忥細鍏�(n猫i)缃ぇ閲� CLB锛圕onfigurable Logic Block锛�銆丅lock RAM 鍜� DSP Slice锛屾豢瓒冲京(f霉)闆滅殑绠楁硶鍜屾暩(sh霉)鎿�(j霉)铏曠悊闇€姹�銆�
銆€銆€3. 楂橀€熸帴鍙ｆ敮鎸侊細鏀寔楂橀仈(d谩) 32Gbps 鐨勬敹鐧�(f膩)鍣ㄩ€熺巼锛屽苟鍏煎 PCIe Gen4銆丆CIX 鍜� CXL 绛夊崝(xi茅)璀�銆�
銆€銆€4. 瀹夊叏鍔熻兘锛氭彁渚� AES-256 鍔犲瘑鍜� SHA-356 瑾�(r猫n)璀変互淇濊(h霉) IP 鍜岄厤缃暩(sh霉)鎿�(j霉)銆�
銆€銆€5. 鍙潬鎬э細闆嗘垚鑷仼鎳�(y墨ng)鍧囪　鍜屽墠鍚戠尘閷�(cu貌)鍔熻兘锛岀⒑淇濇暩(sh霉)鎿�(j霉)鍌宠几?sh霉)鐩吔鍟冩荡?br>銆€銆€6. 闈堟椿鎬э細鏀寔澶氱ó閰嶇疆鏂瑰紡鍜屽嫊(d貌ng)鎱�(t脿i)閮ㄥ垎閲嶉厤缃妧琛�(sh霉)锛屾柟渚跨郴绲�(t菕ng)鍗囩礆(j铆)鍜岀董璀�(h霉)銆�

鎳�(y墨ng)鐢�

瑭� FPGA 寤ｆ硾鎳�(y墨ng)鐢ㄤ簬浠ヤ笅闋�(l菒ng)鍩燂細
銆€銆€1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庢湇鍕�(w霉)鍣ㄥ姞閫�銆佺恫(w菐ng)绲�(lu貌)瀹夊叏鍜屽瓨鍎�(ch菙)瑙ｆ焙鏂规銆�
銆€銆€2. 閫氫俊瑷�(sh猫)鍌欙細鏀寔 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙(j墨)绛夌恫(w菐ng)绲�(lu貌)鍩虹(ch菙)瑷�(sh猫)鏂�銆�
銆€銆€3. 瑕栭牷鑸囧湒鍍忚檿鐞嗭細瀵�(sh铆)鐝�(xi脿n)瀵�(sh铆)鏅�(sh铆)瑕栭牷绶ㄨВ纰笺€佸湒鍍忓寮�(qi谩ng)鍜岃▓(j矛)绠楁(j墨)瑕栬鍔熻兘銆�
銆€銆€4. 宸ユキ(y猫)鑷嫊(d貌ng)鍖栵細鎻愪緵绮剧⒑鎺у埗鍜岄珮鏁堟暩(sh霉)鎿�(j霉)閲囬泦鑳藉姏銆�
銆€銆€5. 閱�(y墨)鐧傝ō(sh猫)鍌欙細鐢ㄤ簬瓒呰伈娉㈡垚鍍忋€佸(sh铆)鏅�(sh铆)淇¤櫉(h脿o)铏曠悊鍜岃ê鏂疯ō(sh猫)鍌欓枊鐧�(f膩)銆�
銆€銆€6. 姹借粖闆诲瓙锛氭敮鎸侀珮绱�(j铆)椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛夊拰鑷嫊(d貌ng)椐曢鍔熻兘銆�