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XCVU13P-3FHGC2104E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛岄噰鐢� 16nm FinFET 宸ヨ棟鍒堕�犮�傝┎鑺墖閬╃敤浜庨珮鎬ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熶互鍙婂湒鍍忚檿鐞嗙瓑闋樺煙銆�
銆�銆�瑭插瀷铏熶腑鐨� XCVU 琛ㄧず灞簬 Virtex UltraScale+ 绯诲垪锛�13P 琛ㄦ槑鍏惰硣婧愯(gu墨)妯″拰椤炲瀷锛屾暩(sh霉)瀛� 3 浠ｈ〃閫熷害绛夌礆锛孎(xi脿n)HGC2104 琛ㄧず灏佽椤炲瀷鐐� 2104 寮曡叧鐨� BGA 灏佽锛孍 琛ㄧず鍟嗙敤绱氭韩搴﹁寖鍦嶃��
绯诲垪锛歏irtex UltraScale+
銆�銆�鍨嬭櫉锛歑CVU13P-3FHGC2104E
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 2,050,000 鍊�
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 7,800 鍊�
銆�銆�Block RAM 瀹归噺锛氱磩 68 Mbit
銆�銆�UltraRAM 瀹归噺锛氱磩 72 Mbit
銆�銆�Transceiver 鏁�(sh霉)鎿�(j霉)閫熺巼锛氭渶楂� 32.75 Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1,440 鍊�
銆�銆�灏佽椤炲瀷锛欶HGC2104 (2104 寮曡叧 BGA)
銆�銆�宸ヤ綔婧害鑼冨湇锛�0掳C 鑷� 85掳C (鍟嗙敤绱�)
XCVU13P-3FHGC2104E 鎻愪緵浜嗗挤澶х殑鍙法绋嬮倧杓硣婧愬拰璞愬瘜鐨勭‖鏍� IP 妯″锛屾敮鎸� PCIe Gen4銆丆CIX 鍜屼互澶恫(w菐ng)绛夊姛鑳�銆傚畠閭勫叿鍌欓珮鏁堢殑鏁�(sh霉)鎿�(j霉)铏曠悊鑳藉姏锛岄仼鍚堥渶瑕侀珮甯跺鍜屼綆寤堕伈鐨勬噳鐢ㄥ牬鏅�銆�
銆�銆�姝ゅ锛岃┎鍣ㄤ欢鍏�(n猫i)缃殑 HBM (High Bandwidth Memory) 鏀寔鍔熻兘锛堝湪鏌愪簺鐗堟湰涓級锛岃兘澶犳彁渚涙サ楂樼殑瀛樺劜鍣ㄥ付瀵�锛屾豢瓒虫鍣ㄥ缈掋�佹暩(sh霉)鎿�(j霉)鍒嗘瀽绛夋噳鐢ㄧ殑闇�姹�銆�
銆�銆�鍚屾檪锛岃┎鑺墖閲囩敤浜嗗爢鐤婄鐗囦簰鑱�(li谩n)鎶�琛�(sh霉) (SSI)锛屽鐝�(xi脿n)浜嗘洿灏忕殑灏哄鍜屾洿楂樼殑闆嗘垚搴�銆傞�欎娇寰楀畠鍙互杓曟澗鎳夊皪寰╅洔鐨勭郴绲�(t菕ng)瑷▓闇�姹傦紝鍚屾檪闄嶄綆鏁撮珨鍔熻�楀拰鎴愭湰銆�
銆�銆�闁嬬櫦(f膩)浜哄摗鍙互鍒╃敤 Vivado Design Suite 宸ュ叿閺堝皪閫欐 FPGA 閫茶瑷▓銆侀璀夊拰鍎�(y艒u)鍖�锛屽緸鑰屽姞蹇敘(ch菐n)鍝佷笂甯傛檪闁�銆�
瑭� FPGA 甯哥敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 楂樻�ц兘瑷堢畻 (HPC)锛屼緥濡傞噾铻嶅缓妯″拰鍩哄洜绲勫鍒嗘瀽銆�
銆�銆�2. 缍�(w菐ng)绲″熀绀庤ō鏂斤紝濡� 5G 鐒＄窔鍩虹珯鍜屾牳蹇冭矾鐢卞櫒銆�
銆�銆�3. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜� AI 鎺ㄧ悊鍜屽叾浠栧京闆滈亱绠椾换鍕�銆�
銆�銆�4. 瑕栭牷杞�(zhu菐n)纰艰垏鍦栧儚铏曠悊锛屾秹鍙婂鏅傝闋绘祦濯掗珨鏈嶅嫏銆�
銆�銆�5. 宸ユキ(y猫)鑷嫊鍖栨帶鍒讹紝鐗瑰垾鏄湪闇�瑕侀潏娲婚厤缃� IO 鍜屽崝(xi茅)璀拌綁(zhu菐n)鎻涚殑鎯呮硜涓�銆�
銆�銆�XCVU13P-3FHGC2104E 鐨勯珮甯跺銆佷綆寤堕伈鐗规�т娇鍏舵垚鐐鸿ū澶氶珮绔噳鐢ㄧ殑鐞嗘兂閬告搰銆�
XCVU13P-2FHGB2104E
銆�銆�XCVU13P-3FLVA2104E
銆�銆�XCVU13P-3EHBG1579F
