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XCVU5P-3FLVB2104E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鍣ㄤ欢涓殑涓�鍊嬪瀷铏�銆傝┎绯诲垪鍩轰簬鍏堥�茬殑 FinFET 宸ヨ棟鎶�琛�(sh霉)锛屾彁渚涢珮鎬ц兘銆佷綆鍔熻�楀拰楂橀倧杓瘑搴︾殑瑙ｆ焙鏂规銆傛鍣ㄤ欢寤ｆ硾鎳夌敤浜庨�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熴�佸湒鍍忚檿鐞�銆佸伐妤�(y猫)鑷嫊鍖栦互鍙婅埅绌鸿埅澶╃瓑闋樺煙銆�
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鑺墖椤炲瀷锛欶PGA
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 250 钀��
銆�銆�DSP Slice 鏁�(sh霉)閲忥細7800 鍊�
銆�銆�Block RAM 瀹归噺锛氱磩 39.7MB
銆�銆�閰嶇疆 Flash锛氱劇鍏�(n猫i)缃�
銆�銆�I/O 鏁�(sh霉)閲忥細鏈�澶� 1224 鍊�
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹� 0.85V
銆�銆�灏佽椤炲瀷锛歀VB2104
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�鍔熻�楀吀鍨嬪�硷細绱� 10W锛堝彇姹轰簬浣跨敤鍫存櫙锛�
XCVU5P-3FLVB2104E 鎻愪緵鍗撹秺鐨勬�ц兘鑸囬潏娲绘��锛屽叾涓昏鐗规�у寘鎷細
銆�銆�1. 闆嗘垚澶ч噺鍙法绋嬮倧杓柈鍏�锛岄仼鐢ㄤ簬寰╅洔瑷堢畻浠诲嫏锛�
銆�銆�2. 鍏�(n猫i)宓岄珮鏁堢殑 DSP 妯″锛岃兘澶犳豢瓒抽珮绮惧害鏁�(sh霉)瀛椾俊铏熻檿鐞嗛渶姹�锛�
銆�銆�3. 鏀寔澶氶�熺巼鐨勯珮閫熶覆琛屾敹鐧�(f膩)鍣�锛屽偝杓搁�熷害鏈�楂樺彲閬� 32.75Gbps锛�
銆�銆�4. 寮峰ぇ鐨勬檪閻樼鐞嗗伐鍏� (Clock Management Tile)锛岀⒑淇濈簿纰虹殑鏅傞悩鍒嗙櫦(f膩)鍜岀浉浣嶈(di脿o)鏁达紱
銆�銆�5. 澶氱ó瀛樺劜鎺ュ彛鏀寔锛屼緥濡� DDR4銆丩PDDR4 鍜� HBM锛�
銆�銆�6. 鎻愪緵澶氱ó闆绘簮绠＄悊妯″紡浠ュ劒(y艒u)鍖栬兘鏁�锛�
銆�銆�7. 寤ｆ硾鍏煎鍚勭ó澶栭儴鍗�(xi茅)璀帮紝濡� PCIe Gen4銆丆CIX 鍜� CXL銆�
閫欐 FPGA 鑺墖閬╃敤浜庝互涓嬮牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庤矤杓夊潎琛�銆佺恫(w菐ng)绲″姞閫熷拰娣卞害瀛哥繏鎺ㄧ悊绛変换鍕欙紱
銆�銆�2. 閫氫俊绯荤当(t菕ng)锛氭敮鎸� 5G 鐒＄窔鍩虹瑷柦涓殑鍩哄付铏曠悊鍜屽墠鍌�/鍥炲偝缍�(w菐ng)绲″姛鑳�锛�
銆�銆�3. 鍦栧儚铏曠悊锛氬湪瑕栭牷绶ㄧ⒓瑙ｇ⒓銆佸湒鍍忓寮峰強瀵︽檪鍒嗘瀽涓櫦(f膩)鎻棞閸典綔鐢�锛�
銆�銆�4. 宸ユキ(y猫)鎺у埗锛氬鐝�(xi脿n)閬嬪嫊鎺у埗銆佹鍣ㄤ汉瑕栬鍙婂叾浠栧京闆滅殑宸ユキ(y猫)鑷嫊鍖栨噳鐢�锛�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細鐢ㄤ綔淇¤櫉铏曠悊鍠厓鎴栧祵鍏ュ紡鎺у埗绯荤当(t菕ng)鐨勬牳蹇冪祫浠�锛�
銆�銆�6. 閱�(y墨)鐧傝ō鍌欙細鎻愪緵楂樼簿搴︽暩(sh霉)鎿�(j霉)閲囬泦鍜屽鏅傚湒鍍忛噸寤鸿兘鍔�銆�
XCVU5P-2FLGA2104E
銆�銆�XCVU5P-3EHBG757I
銆�銆�XCVU5P-3FHGB2104E
