鏅傞枔锛�2025/4/27 19:14:49
闁辫畝锛�34
XCVU7P-1FLGA2104C 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜� 16nm FinFET 鍒剁▼宸ヨ棟鍒堕��銆傝┎鍣ㄤ欢灞簬 Virtex UltraScale+ 绯诲垪涓殑楂樻�ц兘鍨嬭櫉锛屽叿鏈夊ぇ瑕�(gu墨)妯￠倧杓硣婧�銆侀珮閫熸敹鐧�(f膩)鍣ㄥ拰璞愬瘜鐨勫瓨鍎插櫒璩囨簮锛岄仼鍚堢敤浜庨珮甯跺閫氫俊绯荤当(t菕ng)銆侀珮绱氫俊铏熻檿鐞嗕互鍙婃暩(sh霉)鎿�(j霉)涓績鍔犻�熺瓑鎳夌敤鍫存櫙銆�
銆�銆�鍏跺皝瑁濆舰寮忕偤 FLGA2104锛屽叿鏈夊嚭鑹茬殑鏁ｇ啽鎬ц兘鍜岄浕姘ｇ壒鎬�锛岃兘澶犳豢瓒冲京闆滆ō瑷堢殑闇�姹傘��
鍨嬭櫉锛歑CVU7P-1FLGA2104C
銆�銆�绯诲垪锛歏irtex UltraScale+
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓锛氱磩 200 钀��
銆�銆�DSP Slice 鏁�(sh霉)閲忥細5880
銆�銆�Block RAM锛氱磩 59.5 MB
銆�銆�UltraRAM锛氱磩 9.3 MB
銆�銆�I/O 寮曡叧鏁�(sh霉)閲忥細2104
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄦ暩(sh霉)閲忥細64
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75 Gbps
銆�銆�渚涢浕闆诲锛�0.85V 鏍稿績闆诲 / 1.0V I/O 闆诲
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�灏佽褰㈠紡锛欶LGA2104
XCVU7P-1FLGA2104C 鎿佹湁寮峰ぇ鐨勭‖浠舵灦妲�锛屾敮鎸佸绋厛閫茬壒鎬э細
銆�銆�1. 楂橀�熶覆琛屾敹鐧�(f膩)鍣細鎻愪緵楂橀仈 32.75 Gbps 鐨勬暩(sh霉)鎿�(j霉)鍌宠几閫熺巼锛岄仼鍚堢敤浜庨珮閫熼�氫俊鎺ュ彛锛屽 PCIe Gen4 鍜屼互澶恫銆�
銆�銆�2. 澶ц(gu墨)妯￠倧杓硣婧愶細瓒呴亷 200 钀�嬮倧杓柈鍏�锛屽彲浠ュ鐝�(xi脿n)寰╅洔鐨勬暩(sh霉)瀛楅浕璺ō瑷�銆�
銆�銆�3. 灏堢敤 DSP 妯″锛氬収缃� 5880 鍊� DSP Slice锛岃兘澶犻珮鏁堝畬鎴愭诞榛為亱绠楀拰鐭╅櫍涔樻硶绛変换鍕�銆�
銆�銆�4. 鍏у祵瀛樺劜鍣細鍖呭惈绱� 59.5 MB 鐨� Block RAM 鍜� 9.3 MB 鐨� UltraRAM锛屾敮鎸佸ぇ瀹归噺鏁�(sh霉)鎿�(j霉)绶╂矕銆�
銆�銆�5. 鏀寔闈堟椿鐨勬檪閻樼鐞嗭細閫氶亷闆嗘垚 PLL 鍜� MMCM锛屽彲浠ョ敓鎴愮簿纰虹殑鏅傞悩淇¤櫉锛屾豢瓒充笉鍚屾ā濉婄殑闇�姹�銆�
銆�銆�6. 瀹夊叏鎬у姛鑳斤細鏀寔 AES 鍜� SHA 鍔犲瘑绠楁硶锛屼繚璀� IP 鏍稿拰閰嶇疆鏁�(sh霉)鎿�(j霉)鐨勫畨鍏ㄣ��
銆�銆�7. 鍔熻�楀劒(y艒u)鍖栵細閲囩敤鍕曟厠(t脿i)鍔熻�楃鐞嗘妧琛�锛屽彲浠ユ牴鎿�(j霉)瀵﹂殯璨犺級瑾挎暣鑺墖鐨勫伐浣滅媭鎱�(t脿i)锛岄檷浣庢暣楂旇兘鑰�銆�
XCVU7P-1FLGA2104C 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘瑷堢畻鍜岄珮甯跺閫氫俊鐨勯牁鍩燂細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浣滃姞閫熷崱鐨勬牳蹇冨櫒浠讹紝鍩�(zh铆)琛屾繁搴﹀缈掓帹鐞�銆佽闋昏綁纰煎拰鏁�(sh霉)鎿�(j霉)澹撶府绛変换鍕欍��
銆�銆�2. 缍茬怠閫氫俊锛氶仼鐢ㄤ簬 5G 鍩虹珯銆佽矾鐢卞櫒鍜屼氦鎻涙绛夎ō鍌�锛屾彁渚涢珮閫熸暩(sh霉)鎿�(j霉)杞夌櫦(f膩)鑳藉姏銆�
銆�銆�3. 閱�(y墨)鐧傚奖鍍忥細鐢ㄤ簬瀵︽檪鍦栧儚铏曠悊鍜屽垎鏋�锛屾敮鎸� CT銆丮RI 绛夐珮绔啱(y墨)鐧傝ō鍌�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栵細鍦ㄥ伐妤�(y猫)鎺у埗鍜屾鍣ㄤ汉闋樺煙涓紝璨犺铂寰╅洔绠楁硶鐨勯亱琛屽拰瀵︽檪闊挎噳銆�
銆�銆�5. 鑸┖鑸ぉ锛氭豢瓒抽珮鍙潬鎬ц姹傜殑鐠�(hu谩n)澧冧腑锛屽煼(zh铆)琛岄棞閸典换鍕欑殑淇¤櫉铏曠悊鍜屾暩(sh霉)鎿�(j霉)鍌宠几銆�
XCVU5P-1FLGA2104E, XCVU9P-1FLGA2104I
