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XCVU7P-L2FLVA2104E 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖銆傝┎绯诲垪閲囩敤鍏堥�茬殑 FinFET 宸ヨ棟鎶�琛擄紝鏃ㄥ湪鐐洪珮鎬ц兘瑷堢畻銆佺恫(w菐ng)绲￠�氫俊銆佹暩(sh霉)鎿�(j霉)涓績鍔犻�熶互鍙婇珮绔祵鍏ュ紡铏曠悊绛夋噳鐢ㄦ彁渚涘挤澶х殑鍙法绋嬮倧杓拰闈堟椿鐨� I/O 鏀寔銆�
銆�銆�姝ゅ瀷铏熷爆浜� Virtex UltraScale+ HBM 绯诲垪锛岄泦鎴愪簡楂樺付瀵瓨鍎插櫒锛圚BM锛�锛岃兘澶犲鐝�(xi脿n)瓒呴珮鐨勬暩(sh霉)鎿�(j霉)鍚炲悙閲忓拰浣庡欢閬叉�ц兘銆傞�氶亷灏� FPGA 鍜� HBM 闆嗘垚鍦ㄥ悓涓�灏佽涓�锛岄’钁楁笡灏戜簡鍏�(n猫i)瀛樿í鍟忕摱闋革紝骞堕仼鐢ㄤ簬闇�瑕佸ぇ閲忔暩(sh霉)鎿�(j霉)铏曠悊鐨勬噳鐢ㄥ牬鏅�銆�
鑺墖绯诲垪锛歏irtex UltraScale+ HBM
銆�銆�宸ヨ棟绡�(ji茅)榛烇細16nm
銆�銆�FPGA鏋舵锛歎ltraScale+
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 350 钀�嬬郴绲�(t菕ng)閭忚集鍠厓
銆�銆�RAM瀹归噺锛氱磩 89MB 宓屽叆寮忓RAM
銆�銆�DSP Slice鏁�(sh霉)閲忥細绱� 8400鍊�
銆�銆�I/O鏁�(sh霉)閲忥細鏈�澶氭敮鎸� 2104 鍊嬬敤鎴禝/O
銆�銆�渚涢浕闆诲锛氭牳蹇冮浕澹�1.0V
銆�銆�灏佽椤炲瀷锛歀2FLVA
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�HBM瀹归噺锛氭渶楂樻敮鎸� 8GB HBM2
銆�銆�HBM甯跺锛氶珮閬� 460 GB/s
XCVU7P-L2FLVA2104E 鎻愪緵浜嗗崜瓒婄殑鎬ц兘鍜岄潏娲绘�э紝涓昏鐗规�у寘鎷細
銆�銆�1. 楂樺瘑搴﹂倧杓硣婧�锛岄仼鍚堝京闆滅殑鏁�(sh霉)瀛椾俊铏熻檿鐞嗕换鍕欍��
銆�銆�2. 闆嗘垚楂樺付瀵瓨鍎插櫒 (HBM)锛岄’钁楁彁鍗囦簡鐗囦笂瀛樺劜鍣ㄧ殑瑷晱閫熷害銆�
銆�銆�3. 澶氶仈 8400 鍊� DSP Slice锛岀敤浜庨珮鏁堝鐝�(xi脿n)娴粸閬嬬畻鍜岀煩闄ｄ箻娉曠瓑鎿嶄綔銆�
銆�銆�4. 鏀寔澶氱ó楂橀�熶覆琛屾敹鐧�(f膩)鍣ㄦ婧栵紝鍌宠几閫熺巼鍙仈 32.75 Gbps銆�
銆�銆�5. 鍏�(n猫i)缃睈瀵岀殑澶栬ō鎺ュ彛 IP 鏍�锛屽 PCIe Gen4銆丆CIX 鍜屼互澶恫(w菐ng) MAC銆�
銆�銆�6. 鎻愪緵寮峰ぇ鐨勫畨鍏ㄥ姛鑳�锛屽寘鎷� AES-256 鍔犲瘑鍜� RSA 绨藉悕椹楄瓑銆�
銆�銆�7. 鏀寔鍕曟厠(t脿i)鍔熻兘鍒囨彌 (DFX) 鎶�琛�锛屽厑瑷遍儴鍒嗛噸閰嶇疆浠ュ劒(y艒u)鍖栧姛鑰楀拰鎬ц兘銆�
銆�銆�8. 鐗囦笂瑾�(di脿o)瑭﹀拰鍒嗘瀽宸ュ叿闆嗘垚锛屼究浜庨枊鐧�(f膩)鍜岀董璀�銆�
銆�銆�閫欎簺鐗规�т娇鍏堕潪甯搁仼鍚堢敤浜庢鍣ㄥ缈掓帹鐞嗗姞閫�銆佽闋诲湒鍍忚檿鐞�銆佺恫(w菐ng)绲″寘鍒嗛鍜屽ぇ鏁�(sh霉)鎿�(j霉)鍒嗘瀽绛夐牁鍩熴��
瑭茶姱鐗囧唬娉涙噳鐢ㄤ簬浠ヤ笅闋樺煙锛�
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�燂細鍙敤浜庢暩(sh霉)鎿�(j霉)搴煡瑭㈠姞閫�銆佹暩(sh霉)鎿�(j霉)澹撶府/瑙ｅ绺互鍙婄恫(w菐ng)绲″畨鍏ㄨ檿鐞�銆�
銆�銆�2. 楂樻�ц兘瑷堢畻 (HPC)锛氭敮鎸佺瀛歌▓绠�銆佸熀鍥犵祫瀛哥爺绌跺拰閲戣瀺寤烘ā銆�
銆�銆�3. 缍�(w菐ng)绲￠�氫俊锛氶仼鐢ㄤ簬璺敱鍣�銆佷氦鎻涙鍜岀劇绶氬熀绔欎腑鐨勬暩(sh霉)鎿�(j霉)鍖呰檿鐞嗗拰鍗�(xi茅)璀拌綁鎻�銆�
銆�銆�4. 瑕栭牷铏曠悊锛氬鐝�(xi脿n)瀵︽檪瑕栭牷绶ㄧ⒓銆佽В纰煎拰澧炲挤鍔熻兘銆�
銆�銆�5. 鑷嫊椐曢鑸嘇DAS锛氱敤浜庡偝鎰熷櫒铻嶅悎鍜岃▓绠楁瑕栬绠楁硶鍔犻��銆�
銆�銆�6. 閱�(y墨)鐧傝ō鍌欙細鏀寔閱�(y墨)瀛稿奖鍍忛噸寤哄拰瀵︽檪鏁�(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�鍏堕珮甯跺瀛樺劜鍣ㄥ拰澶ц(gu墨)妯″苟琛岃▓绠楄兘鍔涗娇寰楀畠鍦ㄩ渶瑕佸揩閫熸暩(sh霉)鎿�(j霉)铏曠悊鍜屽京闆滅畻娉曞煼(zh铆)琛岀殑鍫存櫙涓嬭〃鐝�(xi脿n)鍎�(y艒u)鐣�銆�
XCVU9P-2LFLVA2104E
銆�銆�XCVU5P-2LFLVA2104E
