鏅傞枔锛�2025/5/7 20:06:51
闁辫畝锛�29
XCVU9P-3FLGB2104E 鏄敱 Xilinx 鍏徃鐢熺敘鐨� UltraScale+ 绯诲垪楂樼 FPGA 鑺墖锛屽熀浜庤嚭绌嶉浕 16nm 鍒剁▼宸ヨ棟鍒堕�犮�傝┎鍨嬭櫉涓昏闈㈠悜楂樺付瀵�銆侀珮鎬ц兘瑷堢畻鍜屽京闆滅郴绲�(t菕ng)闆嗘垚鐨勬噳鐢ㄥ牬鏅�锛屽唬娉涙噳鐢ㄤ簬鏁告摎涓績鍔犻��銆佺恫绲¤檿鐞嗐�佷汉宸ユ櫤鑳芥帹鐞嗕互鍙婂伐妤�(y猫)鑷嫊鍖栫瓑闋樺煙銆�
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绯诲垪锛歎ltraScale+
銆�銆�灏佽锛欶LGB2104
銆�銆�鍒剁▼锛�16nm
銆�銆�閰嶇疆妯″紡锛歋lave SPI / Master SPI / BPI / HSWAP
銆�銆�閭忚集鍠厓锛氱磩 570 钀��
銆�銆�DSP 妯″锛�3220 鍊�
銆�銆�RAM 璩囨簮锛殈68MB 鍒嗗竷寮� RAM + 濉� RAM
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
銆�銆�I/O 閵�琛屾暩閲忥細54 鍊�
銆�銆�渚涢浕闆诲鑼冨湇锛�0.8V 鏍稿績闆诲锛�1.0V 杓斿姪闆诲
XCVU9P-3FLGB2104E 鎻愪緵浜嗛珮搴﹀彲鎿村睍鐨勭‖浠舵灦妲嬶紝鍏锋湁寮峰ぇ鐨勯倧杓檿鐞嗚兘鍔涘拰楂樻晥鐨勬暩瀛椾俊铏熻檿鐞嗘�ц兘銆傚畠鏀寔闈堟椿鐨勬檪閻樼鐞嗗姛鑳斤紝鍏峰倷澶氳矾 PLL 鍜� MMCM锛堟贩鍚堟ā寮忔檪閻樼鐞嗗櫒锛�锛屽彲浠ョ簿纰虹敓鎴愬悇绋牷鐜囩殑鏅傞悩淇¤櫉銆�
銆�銆�姝ゅ锛岃┎鑺墖鍏х疆浜嗗ぇ閲忕殑纭牳 IP锛屼緥濡� 100G 浠ュお缍� MAC銆両nterlaken銆丳CIe Gen4 鎺у埗鍣ㄧ瓑锛屾サ澶у湴娓涘皯浜嗚ō瑷堝懆鏈熷拰闁嬬櫦(f膩)鎴愭湰銆傚叾鍔熻�楀劒(y艒u)鍖栨妧琛撻�氶亷鍕曟厠(t脿i)瑾跨瘈(ji茅)宸ヤ綔闆诲鍜岄牷鐜囧鐝句簡浣庡姛鑰楅亱琛�锛屽悓鏅傛彁渚涗簡鍏ㄩ潰鐨勮瑭﹀拰鐩�(ji膩n)鎺у伐鍏蜂互绨″寲闁嬬櫦(f膩)娴佺▼銆�
銆�銆�姝� FPGA 閭勯泦鎴愪簡澶у閲忕殑鐗囦笂瀛樺劜鍣ㄥ拰鍒嗗竷寮忕珐瀛樻鍒�锛岀⒑淇濇暩鎿氬偝杓哥殑楂樺悶鍚愰噺鍜屼綆寤堕伈銆傜祼鍚堣睈瀵岀殑澶栬ō鎺ュ彛鍜屾ā濉婂寲鐨勮ō瑷堢悊蹇�锛孹CVU9P 鎴愮偤瀵︾従楂樻�ц兘宓屽叆寮忕郴绲�(t菕ng)鐨勭悊鎯抽伕鎿�銆�
瑭插瀷铏熼仼鐢ㄤ簬闇�瑕侀珮鎬ц兘骞惰瑷堢畻鑳藉姏鐨勯牁鍩�锛屽锛�
銆�銆�- 鏁告摎涓績鍔犻�熷崱
銆�銆�- 楂橀�熺恫绲′氦鎻涙鍜岃矾鐢卞櫒
銆�銆�- AI 鎺ㄧ悊鍔犻��
銆�銆�- 鍦栧儚铏曠悊鑸囪▓绠楁瑕栬
銆�銆�- 楂橀牷浜ゆ槗绯荤当(t菕ng)
銆�銆�- 宸ユキ(y猫)鎺у埗鑸囨鍣ㄤ汉
銆�銆�- 閱�(y墨)鐧傛垚鍍忚ō鍌�
銆�銆�- 杌婅級鑷嫊椐曢杓斿姪绯荤当(t菕ng)
銆�銆�鎲戝�熷叾鍑鸿壊鐨勯潏娲绘�у拰鍙摯灞曟�э紝XCVU9P-3FLGB2104E 鍦ㄥ鍊嬭妤�(y猫)涓寤ｆ硾閲囩敤銆�
XCVU7P-3FLGB2104E, XCVU13P-3FLGB2104E
