绯诲垪锛歏irtex UltraScale+
銆�銆�鍨嬭櫉锛歑CVU9P-L2FLGC2104E
銆�銆�灏佽�濓細FLGC2104
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�CLB鍒囩墖鏁�(sh霉)閲忥細绱�357,840鍊�
銆�銆�DSP Slice鏁�(sh霉)閲忥細绱�7,140鍊�
銆�銆�Block RAM瀹归噺锛氱磩68MB
銆�銆�UltraRAM瀹归噺锛氱磩27MB
銆�銆�PCIe Gen3閫氶亾鏁�(sh霉)閲忥細鏈�澶�8姊�
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂樺彲閬�32.75Gbps
銆�銆�I/O寮曡叧鏁�(sh霉)閲忥細绱�2104鍊�

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銆�銆�1. 楂樻�ц兘瑷堢畻鑳藉姏锛氶�氶亷澶ч噺鍙�绶ㄧ▼閭忚集鍠�鍏冨拰DSP妯″�婃敮鎸佸��(f霉)闆滄暩(sh霉)瀛�(xu茅)閬嬬畻鍙婁俊铏熻檿鐞�銆�
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銆�銆�閫欎簺鐗归粸浣垮緱XCVU9P鎴愮偤瑷卞�氬墠娌挎妧琛�(sh霉)闋�(l菒ng)鍩熶腑鐨勭悊鎯抽伕鎿囥��

瑭插瀷铏熺殑FPGA閬╃敤浜庝互涓嬪牬鏅�锛�
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銆�銆�XCVU9P-L2FLGC2104E鎲戝�熷挤澶х殑鎬ц兘鍜屽�氬姛鑳芥��锛屽湪涓婅堪鍙婂叾浠栭珮绉戞妧闋�(l菒ng)鍩熷潎琛ㄧ従(xi脿n)鍑鸿壊銆�

XCVU7P-FLGA2104E
銆�銆�XCVU9P-FLGA2104E
銆�銆�XCVU11P-FLGA2104E