鏅傞枔锛�2025/6/6 0:55:36
闁辫畝锛�12
XCZU11EG-2FFVC1760E 鏄� Xilinx锛堣辰闈堟�濓級鍏徃鎺ㄥ嚭鐨� Zynq UltraScale+ MPSoC 绯诲垪涓殑涓�鍊嬮珮绔瀷铏�銆傝┎绯诲垪铻嶅悎浜嗛珮鎬ц兘 FPGA 鏋舵銆佸鏍� ARM 铏曠悊鍣ㄥ拰瀵︽檪铏曠悊鍣紝閬╃敤浜庨渶瑕侀珮瑷堢畻鑳藉姏鑸囬潏娲荤‖浠跺姞閫熺殑鎳夌敤鍫存櫙銆�
銆�銆�XCZU11EG 鍖呭惈寮峰ぇ鐨勮檿鐞嗙郴绲�(t菕ng) (PS) 鍜屽彲绶ㄧ▼閭忚集 (PL)锛岃兘澶犳敮鎸佸京闆滅殑宓屽叆寮忚ō瑷堛�傚叾涓昏鎳夌敤闋樺煙鍖呮嫭宸ユキ(y猫)鑷嫊鍖�銆佹苯杌婇椐涜紨鍔�銆佽闋荤洠(ji膩n)鎺�銆侀�氫俊鍩虹瑷柦绛夈��
灏佽锛欶FVC1760
銆�銆�閫熷害绛夌礆锛�-2
銆�銆�I/O 鏁�(sh霉)閲忥細3456
銆�銆�瀛樺劜鍣ㄥ閲忥細22.5Mb
銆�銆�鏀剁櫦(f膩)鍣ㄩ�熺巼锛�32.75Gbps
銆�銆�宸ヨ棟绡�(ji茅)榛烇細16nm
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
XCZU11EG-2FFVC1760E 鎻愪緵浜嗛潪甯搁珮鐨勯泦鎴愬害鍜屾�ц兘銆�
銆�銆�1. 闆嗘垚浜嗗洓鏍� ARM Cortex-A53 铏曠悊鍣紝鎻愪緵寮峰ぇ鐨勯�氱敤瑷堢畻鑳藉姏銆�
銆�銆�2. 鍏х疆闆欐牳 ARM Cortex-R5 瀵︽檪铏曠悊鍣�锛岄仼鐢ㄤ簬瀵︽檪鎺у埗浠诲嫏銆�
銆�銆�3. FPGA 鍙法绋嬮倧杓崁(q奴)鍩熸搧鏈夎秴閬� 110 钀�嬮倧杓柈鍏冿紝鏀寔寰╅洔绠楁硶鐨勭‖浠跺姞閫�銆�
銆�銆�4. 鏀寔楂橀�熸帴鍙�锛屽 PCIe Gen3銆丏DR4銆丩PDDR4 鍜屽绋� SerDes 鍗�(xi茅)璀般��
銆�銆�5. 楂樻晥鐨勯浕婧愮鐞嗘柟妗堝拰鍔熻�楀劒(y艒u)鍖栬ō瑷堜娇鍏堕仼鍚堝皪鑳芥晥瑕佹眰杓冮珮鐨勬噳鐢ㄧ挵(hu谩n)澧�銆�
銆�銆�6. 鍏х疆鍔犲瘑寮曟搸鍜屽畨鍏ㄥ暉鍕曞姛鑳�锛屼繚闅滅郴绲�(t菕ng)瀹夊叏鎬с��
XCZU11EG-2FFVC1760E 寤ｆ硾鎳夌敤浜庡鍊嬮珮绉戞妧闋樺煙锛�
銆�銆�1. 宸ユキ(y猫)鐗╄伅(li谩n)缍�(w菐ng)锛氱敤浜庡伐妤�(y猫)鎺у埗鍣�銆佹鍣ㄤ汉浠ュ強閭婄罚瑷堢畻瑷倷銆�
銆�銆�2. 姹借粖闆诲瓙锛氭敮鎸� ADAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛�銆佷俊鎭妯傜郴绲�(t菕ng)鍜岃嚜鍕曢椐涘钩鑷恒��
銆�銆�3. 瑕栭牷铏曠悊锛氱敤浜庤闋荤法纰�銆佽В纰笺�佸湒鍍忓寮峰強瑷堢畻姗熻瑕虹浉闂滅殑鎳夌敤銆�
銆�銆�4. 閫氫俊瑷倷锛氬湪 5G 鍩虹珯銆佸皬鍨嬭渹绐╃恫(w菐ng)闂滃拰鍏朵粬鐒＄窔閫氫俊鍩虹瑷柦涓櫦(f膩)鎻棞閸典綔鐢�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忥細鐐鸿秴鑱叉尝銆丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傝ō鍌欐彁渚涢珮鎬ц兘鏁�(sh霉)鎿�(j霉)铏曠悊鑳藉姏銆�
XCZU11EG-1FFVC1760E
銆�銆�XCZU9EG-2FFVC1760E
銆�銆�XCZU7EV-2FFVC1140E
