绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�鍒剁▼宸ヨ棟锛�16nm
銆�銆�FPGA 閭忚集鍠�鍏冩��(sh霉)閲忥細绱� 115K
銆�銆�ARM Cortex-A53 鏍稿績鏁�(sh霉)锛氬洓鏍�
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銆�銆�GPU锛� Mali-400 MP2
銆�銆�瀛樺劜鍣ㄦ帴鍙ｏ細DDR4/LPDDR4
銆�銆�鏈�澶ч牷鐜囷細瓒呴亷 1GHz锛堝彇姹轰簬鍏烽珨閰嶇疆锛�
銆�銆�灏佽�濋�炲瀷锛欶FG1156
銆�銆�宸ヤ綔婧�搴﹁寖鍦嶏��-40掳C 鑷� +85掳C
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銆�銆�PCIe 鏀�鎸侊細Gen3 x8
銆�銆�瑕栭牷绶ㄨВ纰硷細H.264/H.265

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銆�銆�1. 楂樺害闆嗘垚鐨勬灦妲�(g貌u)锛屽寘鍚� ARM 铏曠悊鍣ㄥ瓙绯荤当(t菕ng)鍜� FPGA 鍙�绶ㄧ▼閭忚��锛屼娇寰楃‖浠跺姞閫熷拰杌熶欢閬嬭�岃兘澶犵劇绺�鍗�(xi茅)浣�銆�
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XCZU11EG-L2FFVC1156E 鐨勫挤澶ф�ц兘鍜岃睈瀵屽姛鑳戒娇鍏跺唬娉涙噳(y墨ng)鐢ㄤ簬澶氬�嬮牁(l菒ng)鍩燂細
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XCZU11EG-FFVC1156, XCZU10EG-L2FFVC1156E, XCZU9EG-L2FFVC1156E