鏅傞枔锛�2025/5/7 17:56:47
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绯诲垪锛歓ynq UltraScale+ MPSoC
銆�銆�鍨嬭櫉锛歑CZU17EG
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�灏佽锛欶FVB1517
銆�銆�婧害鑼冨湇锛�0掳C 鑷� 85掳C (鍟嗙敤绱�)
銆�銆�铏曠悊鍣細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�FPGA 閭忚集鍠厓锛氱磩 269K
銆�銆�DSP 妯″鏁�(sh霉)閲忥細2496
銆�銆�瀛樺劜鍣細楂橀仈 24.6 Mb 宓屽叆寮忓瓨鍎插櫒
銆�銆�I/O 鏁�(sh霉)閲忥細澶氶仈 2154 鍊嬬敤鎴� I/O
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銆�銆�闆绘簮闆诲锛氭牳蹇冮浕澹� 0.85V锛孖/O 闆诲鏍规摎(j霉)閰嶇疆涓嶅悓鍙伕 1.8V/2.5V/3.3V
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銆�銆�灏嶄簬 AI 鍜屾鍣ㄥ缈掓噳鐢�锛孹CZU17EG 鐨勫ぇ閲� DSP 妯″鍙互楂樻晥鍩�(zh铆)琛岀煩闄ｉ亱绠楀拰娴粸瑷堢畻銆�
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銆�銆�鏈�鍚�锛屽叾 16nm 宸ヨ棟鎶�琛�(sh霉)浣垮緱 XCZU17EG 鍦ㄦ�ц兘鍜屽姛鑰椾箣闁撳彇寰椾簡鑹ソ鐨勫钩琛�銆�
XCZU17EG 寤ｆ硾鎳夌敤浜庨渶瑕侀珮鎬ц兘鍜屽鏅傝檿鐞嗚兘鍔涚殑闋�(l菒ng)鍩�锛屼緥濡傦細
銆�銆�1. 宸ユキ(y猫)鑷嫊鍖� - 瀵︾従(xi脿n)寰╅洔鐨勫鏅傛帶鍒跺拰鏁�(sh霉)鎿�(j霉)鍒嗘瀽銆�
銆�銆�2. 姹借粖闆诲瓙 - 鏀寔楂樼礆椐曢杓斿姪绯荤当(t菕ng) (ADAS) 鍜岃嚜鍕曢椐涖��
銆�銆�3. 缍�(w菐ng)绲￠�氫俊 - 鎻愪緵楂橀�熸暩(sh霉)鎿�(j霉)鍌宠几鍜屼俊铏熻檿鐞嗚兘鍔�锛岄仼鐢ㄤ簬 5G 鍩虹珯鍜岄倞绶ｈ▓绠楄ō(sh猫)鍌�銆�
銆�銆�4. 宓屽叆寮忚瑕� - 闆嗘垚鍦栧儚铏曠悊鍜屾繁搴﹀缈掔畻娉�锛岀敤浜庡畨闃茬洠(ji膩n)鎺у拰姗熷櫒浜鸿瑕恒��
銆�銆�5. 閱�(y墨)鐧傝ō(sh猫)鍌� - 鐢ㄤ簬瓒呰伈娉㈣ō(sh猫)鍌�銆丆T 鎺冩弿鍎�鍜屽叾浠栭渶瑕佸揩閫熸暩(sh霉)鎿�(j霉)铏曠悊鐨勯啱(y墨)鐧傚剙鍣�銆�
銆�銆�6. 鑸┖鑸ぉ鍜屽湅闃� - 鎻愪緵楂樺彲闈犳��銆佸鏅傛�у拰瀹夊叏鎬т繚闅�銆�
XCZU17EV-3FFVB1517E
銆�銆�XCZU17EG-2FFVB1517E
銆�銆�XCZU17EG-3FFVC1760E
