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XCZU17EG-L1FFVD1760I鏄疿ilinx鍏徃鎺ㄥ嚭鐨刄ltraScale+绯诲垪楂樼FPGA鍣ㄤ欢锛屽熀浜庤嚭绌嶉浕16nm FinFET+宸ヨ棟鍒堕��銆傝┎鑺墖灞簬Zynq UltraScale+ MPSoC绯诲垪锛岄泦鎴愪簡澶氭牳铏曠悊鍣ㄧ郴绲�(t菕ng)鍜屽彲绶ㄧ▼閭忚集鍠厓锛岄仼鐢ㄤ簬楂樻�ц兘瑷堢畻銆佸祵鍏ュ紡瑕栬銆侀�氫俊鍩虹瑷柦绛夋噳鐢ㄩ牁鍩�銆�
銆�銆�XCZU17EG鍨嬭櫉鍏锋湁寮峰ぇ鐨勮檿鐞嗚兘鍔涗互鍙婅睈瀵岀殑澶栬ō鎺ュ彛锛岃兘澶犳豢瓒冲鏅傛暩(sh霉)鎿�(j霉)铏曠悊鍜屽京闆滅畻娉曞鐝�(xi脿n)鐨勯渶姹�銆�
灏佽锛欶FVD1760
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�I/O寮曡叧鏁�(sh霉)锛�1760
銆�銆�RAM澶�?銆�?3.8Mb
銆�銆�DSP Slice鏁�(sh霉)閲忥細5940
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銆�銆�鍏稿瀷鍔熻�楋細10W锛堣鍏烽珨瑷▓鑰屽畾锛�
銆�銆�鏈�澶х敤鎴禝/Os锛�1166
銆�銆�Transceivers鏁�(sh霉)閲忥細48
銆�銆�Transceiver閫熺巼锛氭渶楂�32.75Gbps
XCZU17EG-L1FFVD1760I鍏峰倷浠ヤ笅涓昏鐗规�э細
銆�銆�1. 闆嗘垚闆欐牳ARM Cortex-A53铏曠悊鍣ㄥ拰闆欐牳ARM Cortex-R5瀵︽檪铏曠悊鍣�锛屾敮鎸佸绋搷浣滅郴绲�(t菕ng)鍜屽鏅備换鍕欍��
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銆�銆�3. 鎻愪緵澶氶仈5940鍊婦SP Slice锛岄仼鍚堥�茶楂樼簿搴︽诞榛為亱绠楁垨淇¤櫉铏曠悊銆�
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銆�銆�7. 鍦ㄤ綆鍔熻�楁ā寮忎笅锛屼粛鑳戒繚鎸佸嚭鑹茬殑鎬ц兘琛ㄧ従(xi脿n)锛岄潪甯搁仼鍚堢Щ鍕曞拰閭婄罚瑷堢畻鍫存櫙銆�
瑭叉FPGA寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 宓屽叆寮忚瑕虹郴绲�(t菕ng)涓�锛岀敤浜庡湒鍍忚檿鐞�銆佺洰妯欐娓拰璀樺垾绛夊姛鑳�銆�
銆�銆�2. 閫氫俊鍩虹瑷柦寤鸿ō锛屼緥濡�5G鍩虹珯涓殑鍓嶅偝/鍥炲偝妯″銆�
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銆�銆�6. 姹借粖椐曢杓斿姪绯荤当(t菕ng)锛圓DAS锛�锛岀偤鐠�(hu谩n)澧冩劅鐭ユ彁渚涚‖浠舵敮鎸�銆�
XCZU17EV-L1FFVC1760I
銆�銆�XCZU19EG-1FFVC1760E
