鏅傞枔锛�2025/4/27 12:49:47
闁辫畝锛�25
XCZU19EG-1FFVE1924I 鏄� Xilinx 鍏徃鎺ㄥ嚭鐨� UltraScale+ 绯诲垪 FPGA 鑺墖锛屽熀浜� 16nm FinFET 鍒剁▼宸ヨ棟鍒堕�犮�傝┎鍣ㄤ欢灏堢偤楂樻�ц兘瑷堢畻銆佺恫绲¤檿鐞嗗拰宓屽叆寮忚瑕虹瓑鎳夌敤瑷▓锛屽叿鏈夐珮閭忚集瀵嗗害銆佽睈瀵岀殑 DSP Slice 鍜屽ぇ瀹归噺鐨勫収閮ㄥ瓨鍎插櫒璩囨簮銆�
銆�銆�瑭插瀷铏熷爆浜� Zynq UltraScale+ MPSoC 绯诲垪锛岃瀺鍚堜簡鍙法绋嬮倧杓�佽檿鐞嗗櫒绯荤当(t菕ng)浠ュ強澶氱ó灏堢敤纭欢鍔犻�熸ā濉�锛屾敮鎸佸鏅傝檿鐞嗗拰楂樺害闈堟椿鐨勮ō瑷堥渶姹�銆�
灏佽锛欶FVE1924
銆�銆�閰嶇疆妯″紡锛氫富寰炴ā寮�
銆�銆�I/O 鏁�(sh霉)閲忥細3048
銆�銆�鐢ㄦ埗鍙敤閭忚集鍠厓锛氱磩 1,705,200
銆�銆�DSP Slice 鏁�(sh霉)閲忥細~11,000
銆�銆�鐗囦笂瀛樺劜鍣細~36MB
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +85掳C
銆�銆�渚涢浕闆诲锛氬鏍镐緵闆伙紙鍏ф牳闆诲 0.85V锛岃紨鍔╅浕婧� 1.0V锛�
XCZU19EG 鎻愪緵妤甸珮鐨勬�ц兘鍜岄潏娲绘�э紝鍏舵牳蹇冨劒(y艒u)鍕㈠寘鎷細
銆�銆�1. 闆嗘垚浜嗗洓鏍� ARM Cortex-A53 铏曠悊鍣ㄥ瓙绯荤当(t菕ng)锛岄仼鍚堥亱琛� Linux 鎴栧叾浠栨搷浣滅郴绲�(t菕ng)銆�
銆�銆�2. 鍖呭惈纭寲鐨勬诞榛為亱绠楀柈鍏冨拰瑕栭牷绶ㄨВ纰煎紩鎿庯紝鑳藉椤憲鎻愬崌澶氬獟楂旇檿鐞嗚兘鍔�銆�
銆�銆�3. 鏀寔楂橀�熸帴鍙ｏ紝濡� PCIe Gen4銆丆CIX 鍜� 100G Ethernet MAC锛岄仼鐢ㄤ簬鏁�(sh霉)鎿�(j霉)涓績鍜岄�氫俊闋樺煙銆�
銆�銆�4. 閰嶅倷澶у閲忓 RAM 鍜屽垎甯冨紡 RAM锛屾豢瓒冲京闆滅畻娉曞皪瀛樺劜鐨勯渶姹�銆�
銆�銆�5. 鍏х疆瀹夊叏鍟熷嫊鍔熻兘锛屼繚闅滆ō鍌欏厤鍙楁儭鎰忚粺浠舵敾鎿�銆�
銆�銆�6. 鍔熻�楀劒(y艒u)鍖栨妧琛擄紝浣垮緱鍦ㄩ珮鎬ц兘鐨勫悓鏅傜董鎸佽純浣庡姛鑰楁按骞�銆�
XCZU19EG 寤ｆ硾鎳夌敤浜庝互涓嬪牬鏅細
銆�銆�1. 鏁�(sh霉)鎿�(j霉)涓績鍔犻�熷崱锛岀敤浜庢鍣ㄥ缈掓帹鐞嗘垨鏁�(sh霉)鎿�(j霉)搴煡瑭㈠劒(y艒u)鍖�銆�
銆�銆�2. 楂橀�熺恫绲′氦鎻涙鑸囪矾鐢卞櫒锛屾彁渚涚窔閫熸暩(sh霉)鎿�(j霉)鍖呰檿鐞嗚兘鍔�銆�
銆�銆�3. 宓屽叆寮忚瑕虹郴绲�(t菕ng)锛屼緥濡傝嚜鍕曢椐涙苯杌婁腑鐨勭洰妯欐娓ā濉�銆�
銆�銆�4. 宸ユキ(y猫)鑷嫊鍖栨帶鍒跺钩鑷猴紝鏁村悎瀵︽檪淇¤櫉閲囬泦鑸囧垎鏋愬姛鑳�銆�
銆�銆�5. 閱�(y墨)鐧傛垚鍍忚ō鍌欙紝濡傝秴鑱叉尝鎺冩弿鍎�鎴� CT 瑷倷涓殑鍦栧儚閲嶅缓鍠厓銆�
銆�銆�6. 鐒＄窔鍩虹瑷柦锛屽寘鎷� 5G 灏忓熀绔欏拰澶ц(gu墨)妯� MIMO 澶╃窔闄ｅ垪銆�
XCZU17EG-1FFVC1760E
銆�銆�XCZU15EG-1FFVC1760E
銆�銆�XCZU11EG-1FFVC1760E
