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鎮ㄥソ锛屾杩庝締鍒扮董搴浕瀛愬競鍫寸恫(w菐ng) 鐧婚寗 | 鍏嶈不(f猫i)娉ㄥ唺

鎮ㄦ墍鍦ㄧ殑浣嶇疆锛�闆诲瓙鍏冨櫒浠堕噰璩肩恫(w菐ng) > IC鐧剧 > XCZU19EG-3FFVD1760E

XCZU19EG-3FFVD1760E 鐧�(f膩)甯冩檪闁� 鏅傞枔锛�2025/4/29 12:26:41 鏌ョ湅 闁辫畝锛�36

XCZU19EG-3FFVD1760E 鏄竴娆剧敱 Xilinx 鍏徃鐢熺敘(ch菐n)鐨勯珮绔� FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁�闄ｅ垪锛夎姱鐗囷紝灞簬 Zynq UltraScale+ MPSoC 绯诲垪銆傝┎绯诲垪闆嗘垚浜嗗挤(qi谩ng)澶х殑 ARM Cortex-A53 铏曠悊鍣ㄥ拰瀵�(sh铆)鏅傝檿鐞嗗柈鍏冿紙RPU锛�锛屽悓鏅傚叿鍌欓珮搴﹂潏娲荤殑鍙法绋嬮倧杓硣婧�锛岄仼鍚堢敤浜庨渶瑕侀珮鎬ц兘瑷�(j矛)绠�銆佸(sh铆)鏅傝檿鐞嗗拰浣庡欢閬茬殑鎳�(y墨ng)鐢ㄥ牬鏅��
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鍙冩暩(sh霉)

灏佽锛欶FVD1760
銆�銆�閫熷害绛夌礆锛�-3
銆�銆�I/O 鏁�(sh霉)閲忥細4272
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 180 钀��
銆�銆�瀛樺劜鍣ㄥ閲忥細楂橀仈(d谩) 68MB 宓屽叆寮� RAM
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 5800 鍊�
銆�銆�宸ヨ棟鍒剁▼锛�16nm
銆�銆�宸ヤ綔婧害鑼冨湇锛�-40掳C 鑷� +100掳C
銆�銆�渚涢浕闆诲锛�1.0V 鏍稿績闆诲锛�1.8V I/O 闆诲

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XCZU19EG 鎻愪緵浜嗛潪甯搁珮鐨勯倧杓瘑搴﹀拰 DSP 鎬ц兘锛岄仼鐢ㄤ簬寰�(f霉)闆滅殑淇¤櫉铏曠悊浠诲嫏(w霉)銆�
銆�銆�瀹冨収(n猫i)宓� ARM Cortex-A53 鍜� Cortex-R5 闆欐牳铏曠悊鍣�锛屾敮鎸佸(sh铆)鏅傛搷浣滅郴绲�(t菕ng)鍜岄�氱敤鎿嶄綔绯荤当(t菕ng)鐨勯亱(y霉n)琛�銆�
銆�銆�姝ゅ锛岃┎鑺墖閭勫叿鏈夐珮甯跺鎺ュ彛锛屽 PCIe Gen3銆丏DR4 鎺у埗鍣�銆佸崈鍏嗕互澶恫(w菐ng)绛�锛屽彲浠ヨ紩鏉鹃�ｆ帴澶栭儴瑷�(sh猫)鍌欐垨缍�(w菐ng)绲�(lu貌)銆�
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XCZU19EG 琚唬娉涙噳(y墨ng)鐢ㄤ簬鐒＄窔閫氫俊鍩虹(ch菙)瑷�(sh猫)鏂姐�佹暩(sh霉)鎿�(j霉)涓績鍔犻��銆佽闋诲唬鎾�銆侀珮绱氶椐涘摗杓斿姪绯荤当(t菕ng)锛圓DAS锛夈�佸伐妤�(y猫)鑷嫊鍖栨帶鍒剁瓑闋�(l菒ng)鍩�銆�
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鏇夸唬鍨嬭櫉

XCZU28DR-2FFVG1760E
銆�銆�XCZU15EG-3FFVC1760E
銆�銆�XCZU21S-2FFVC1760E

xczu19eg-3ffvd1760e鎺ㄨ枽渚涙噳(y墨ng)鍟� 鏇村>

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  • 寤犲晢
  • 灏佽/鎵硅櫉
  • 瑭㈠児

xczu19eg-3ffvd1760e鍙冩暩(sh霉)

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  • 鍍规牸1 : 锟�108,940.93000鎵樼洡
  • 绯诲垪Zynq? UltraScale+? MPSoC EG
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  • RAM 澶у皬256KB
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  • 灏佽/澶栨1760-BBGA锛孎(xi脿n)CBGA
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