鏅傞枔锛�2025/5/8 9:34:28
闁辫畝锛�22
XCZU27DR-1FSVE1156E 鏄竴娆惧熀浜� Xilinx UltraScale+ 鏋舵鐨勯珮绔� FPGA 鑺墖銆傝┎绯诲垪鑺墖閲囩敤浜� 16nm FinFET 宸ヨ棟鍒堕�狅紝鍏锋湁楂樻�ц兘銆佷綆鍔熻�楀拰楂橀泦鎴愬害鐨勭壒榛�銆俋CZU27DR 灞簬 Zynq UltraScale+ MPSoC 绯诲垪锛岄泦鎴愪簡 ARM Cortex-A53 鍜� Cortex-R5 铏曠悊鍣ㄥ収(n猫i)鏍�锛岃兘澶犳豢瓒冲京闆滆▓绠椾换鍕欏拰瀵︽檪鎺у埗鐨勯渶姹�銆�
銆�銆�瑭插瀷铏熼倓鍏峰倷寮峰ぇ鐨勫彲绶ㄧ▼閭忚集璩囨簮銆侀珮閫熸敹鐧�(f膩)鍣ㄤ互鍙婅睈瀵岀殑澶栬ō鎺ュ彛锛岄仼鐢ㄤ簬闇�瑕侀珮鎬ц兘铏曠悊鑳藉姏鑸囬潏娲荤‖浠跺姞閫熺殑鎳夌敤鍫存櫙銆�
宸ヨ棟锛�16nm
銆�銆�閭忚集鍠厓鏁�(sh霉)閲忥細绱� 398K
銆�銆�DSP Slice 鏁�(sh霉)閲忥細绱� 4096
銆�銆�RAM 璩囨簮锛圔lock RAM锛夛細绱� 19.3Mb
銆�銆�楂橀�熸敹鐧�(f膩)鍣ㄩ�熺巼锛氭渶楂� 32.75Gbps
銆�銆�I/O 鏁�(sh霉)閲忥細澶氶仈 1456 鍊�
銆�銆�铏曠悊鍣ㄦ灦妲嬶細闆欐牳 ARM Cortex-A53 + 闆欐牳 ARM Cortex-R5
銆�銆�灏佽椤炲瀷锛欶SVE1156E
銆�銆�宸ヤ綔婧害鑼冨湇锛氬伐妤�(y猫)绱氾紙-40掳C 鑷� +100掳C锛�
XCZU27DR 鎻愪緵浜嗗绋棞閸电壒鎬у拰鍎�(y艒u)鍕細
銆�銆�1. 闆嗘垚澶氭牳铏曠悊鍣ㄧ郴绲�(t菕ng)锛圡PSoC锛�锛屽彲浠ュ鐝�(xi脿n)杌熺‖浠跺崝(xi茅)鍚岃ō瑷�銆�
銆�銆�2. 鏀寔楂橀仈 32.75Gbps 鐨勯珮閫熸敹鐧�(f膩)鍣�锛岄仼鍚堥珮甯跺閫氫俊鎳夌敤銆�
銆�銆�3. 鍏峰倷寮峰ぇ鐨� DSP Slice 璩囨簮锛岄潪甯搁仼鍚堜俊铏熻檿鐞嗗拰姗熷櫒瀛哥繏绛夎▓绠楀瘑闆嗗瀷浠诲嫏銆�
銆�銆�4. 鎻愪緵璞愬瘜鐨勫瑷敮鎸侊紝渚嬪 PCIe Gen3銆乁SB 3.0銆丼ATA 3.0 绛�锛屼究浜庨�ｆ帴鍚勭ó瑷倷銆�
銆�銆�5. 閲囩敤鍏堥�茬殑 16nm 鍒剁▼鎶�琛�锛屽湪鎬ц兘鍜屽姛鑰椾箣闁撳彇寰楄壇濂藉钩琛°��
銆�銆�6. 鍏�(n猫i)缃姞瀵嗗紩鎿庡拰瀹夊叏鍟熷嫊鍔熻兘锛屽寮蜂簡绯荤当(t菕ng)鐨勫畨鍏ㄦ��銆�
銆�銆�7. 鏀寔 Linux 鎿嶄綔绯荤当(t菕ng)鍙婂鏅傛搷浣滅郴绲�(t菕ng)锛圧TOS锛夛紝绨″寲杌熶欢闁嬬櫦(f膩)娴佺▼銆�
閫欐鑺墖寤ｆ硾鎳夌敤浜庡鍊嬮牁鍩燂細
銆�銆�1. 閫氫俊鍩虹瑷柦锛氬 5G 鍩虹珯銆佸洖鍌崇恫(w菐ng)绲¤ō鍌�銆�
銆�銆�2. 鏁�(sh霉)鎿�(j霉)涓績锛氱敤浜庢暩(sh霉)鎿�(j霉)鍖呰檿鐞�銆佸瓨鍎插姞閫熺瓑鍔熻兘銆�
銆�銆�3. 宸ユキ(y猫)鑷嫊鍖栵細瀵︽檪鎺у埗銆佸湒鍍忚檿鐞�銆佹鍣ㄤ汉鎳夌敤銆�
銆�銆�4. 閱�(y墨)鐧傚奖鍍忥細瓒呰伈娉��丆T 鎺冩弿鍎�绛夐啱(y墨)鐧傝ō鍌欑殑鏁�(sh霉)鎿�(j霉)閲囬泦鑸囪檿鐞�銆�
銆�銆�5. 鑸┖鑸ぉ鑸囧湅闃诧細闆烽仈绯荤当(t菕ng)銆佽(w猫i)鏄熼�氫俊銆佸祵鍏ュ紡瑷堢畻姗熴��
銆�銆�6. 姹借粖闆诲瓙锛欰DAS锛堥珮绱氶椐涜紨鍔╃郴绲�(t菕ng)锛�銆佽嚜鍕曢椐涘钩鑷恒��
XCZU28DR-1FSVE1156E, XCZU29DR-1FSVE1156E
